c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
345 lines
10 KiB
C
345 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Sun8i platform dram controller init.
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*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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*/
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/*
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* Note this code uses a lot of magic hex values, that is because this code
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* simply replays the init sequence as done by the Allwinner boot0 code, so
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* we do not know what these values mean. There are no symbolic constants for
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* these magic values, since we do not know how to name them and making up
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* names for them is not useful.
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*
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* The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
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* found in the TI Keystone2 documentation:
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* http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
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* "Table4-2 DDR3 PHY Registers"
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* This may be used as a (possible) reference for future work / cleanups.
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*/
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#include <common.h>
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#include <errno.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/prcm.h>
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#include <linux/delay.h>
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static const struct dram_para dram_para = {
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.clock = CONFIG_DRAM_CLK,
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.type = 3,
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.zq = CONFIG_DRAM_ZQ,
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.odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
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.odt_correction = CONFIG_DRAM_ODT_CORRECTION,
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.para1 = 0, /* not used (only used when tpr13 bit 31 is set */
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.para2 = 0, /* not used (only used when tpr13 bit 31 is set */
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.mr0 = 6736,
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.mr1 = 4,
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.mr2 = 16,
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.mr3 = 0,
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/* tpr0 - 10 contain timing constants or-ed together in u32 vals */
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.tpr0 = 0x2ab83def,
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.tpr1 = 0x18082356,
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.tpr2 = 0x00034156,
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.tpr3 = 0x448c5533,
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.tpr4 = 0x08010d00,
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.tpr5 = 0x0340b20f,
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.tpr6 = 0x20d118cc,
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.tpr7 = 0x14062485,
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.tpr8 = 0x220d1d52,
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.tpr9 = 0x1e078c22,
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.tpr10 = 0x3c,
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.tpr11 = 0, /* not used */
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.tpr12 = 0, /* not used */
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.tpr13 = 0x30000,
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};
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static void mctl_sys_init(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* enable pll5, note the divide by 2 is deliberate! */
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clock_set_pll5(dram_para.clock * 1000000 / 2,
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dram_para.tpr13 & 0x40000);
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/* deassert ahb mctl reset */
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
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/* enable ahb mctl clock */
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
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}
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static void mctl_apply_odt_correction(u32 *reg, int correction)
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{
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int val;
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val = (readl(reg) >> 8) & 0xff;
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val += correction;
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/* clamp */
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if (val < 0)
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val = 0;
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else if (val > 255)
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val = 255;
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clrsetbits_le32(reg, 0xff00, val << 8);
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}
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static void mctl_init(u32 *bus_width)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct sunxi_mctl_phy_reg * const mctl_phy =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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if (dram_para.tpr13 & 0x20)
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writel(0x40b, &mctl_phy->dcr);
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else
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writel(0x1000040b, &mctl_phy->dcr);
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if (dram_para.clock >= 480)
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writel(0x5c000, &mctl_phy->dllgcr);
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else
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writel(0xdc000, &mctl_phy->dllgcr);
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writel(0x0a003e3f, &mctl_phy->pgcr0);
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writel(0x03008421, &mctl_phy->pgcr1);
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writel(dram_para.mr0, &mctl_phy->mr0);
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writel(dram_para.mr1, &mctl_phy->mr1);
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writel(dram_para.mr2, &mctl_phy->mr2);
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writel(dram_para.mr3, &mctl_phy->mr3);
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if (!(dram_para.tpr13 & 0x10000)) {
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clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
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clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
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}
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/*
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* All the masking and shifting below converts what I assume are DDR
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* timing constants from Allwinner dram_para tpr format to the actual
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* timing registers format.
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*/
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writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
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writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
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writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
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(dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
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writel(dram_para.tpr3, &mctl_phy->dtpr0);
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writel(dram_para.tpr4, &mctl_phy->dtpr2);
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writel(0x01000081, &mctl_phy->dtcr);
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if (dram_para.clock <= 240 || !dram_para.odt_en) {
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clrbits_le32(&mctl_phy->dx0gcr, 0x600);
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clrbits_le32(&mctl_phy->dx1gcr, 0x600);
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}
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if (dram_para.clock <= 240) {
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writel(0, &mctl_phy->odtcr);
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writel(0, &mctl_ctl->odtmap);
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}
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writel(((dram_para.tpr5 & 0x0f00) << 12) |
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((dram_para.tpr5 & 0x00f8) << 9) |
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((dram_para.tpr5 & 0x0007) << 8),
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&mctl_ctl->rfshctl0);
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writel(((dram_para.tpr5 & 0x0003f000) << 12) |
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((dram_para.tpr5 & 0x00fc0000) >> 2) |
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((dram_para.tpr5 & 0x3f000000) >> 16) |
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((dram_para.tpr6 & 0x0000003f) >> 0),
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&mctl_ctl->dramtmg0);
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writel(((dram_para.tpr6 & 0x000007c0) << 10) |
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((dram_para.tpr6 & 0x0000f800) >> 3) |
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((dram_para.tpr6 & 0x003f0000) >> 16),
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&mctl_ctl->dramtmg1);
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writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
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((dram_para.tpr7 & 0x0000001f) << 16) |
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((dram_para.tpr7 & 0x000003e0) << 3) |
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((dram_para.tpr7 & 0x0000fc00) >> 10),
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&mctl_ctl->dramtmg2);
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writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
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((dram_para.tpr6 & 0xf0000000) >> 16),
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&mctl_ctl->dramtmg3);
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writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
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((dram_para.tpr8 & 0x00000007) << 16) |
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((dram_para.tpr8 & 0x00000038) << 5) |
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((dram_para.tpr8 & 0x000003c0) >> 6),
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&mctl_ctl->dramtmg4);
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writel(((dram_para.tpr8 & 0x00003c00) << 14) |
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((dram_para.tpr8 & 0x0003c000) << 2) |
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((dram_para.tpr8 & 0x00fc0000) >> 10) |
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((dram_para.tpr8 & 0x0f000000) >> 24),
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&mctl_ctl->dramtmg5);
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writel(0x00000008, &mctl_ctl->dramtmg8);
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writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
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((dram_para.tpr9 & 0x00007c00) << 6) |
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((dram_para.tpr9 & 0x000003e0) << 3) |
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((dram_para.tpr9 & 0x0000001f) >> 0),
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&mctl_ctl->pitmg0);
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setbits_le32(&mctl_ctl->pitmg1, 0x80000);
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writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
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&mctl_ctl->sched);
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writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
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writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
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writel(0x00000000, &mctl_ctl->pimisc);
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writel(0x80000000, &mctl_ctl->upd0);
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writel(((dram_para.tpr9 & 0xffc00000) >> 22) |
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((dram_para.tpr10 & 0x00000fff) << 16),
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&mctl_ctl->rfshtmg);
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if (dram_para.tpr13 & 0x20)
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writel(0x01040001, &mctl_ctl->mstr);
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else
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writel(0x01040401, &mctl_ctl->mstr);
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if (!(dram_para.tpr13 & 0x20000)) {
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writel(0x00000002, &mctl_ctl->pwrctl);
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writel(0x00008001, &mctl_ctl->pwrtmg);
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}
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writel(0x00000001, &mctl_ctl->rfshctl3);
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writel(0x00000001, &mctl_ctl->pimisc);
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/* deassert dram_clk_cfg reset */
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setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
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setbits_le32(&mctl_com->ccr, 0x80000);
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/* zq stuff */
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writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
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writel(0x00000003, &mctl_phy->pir);
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udelay(10);
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mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
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writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
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writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
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/* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
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writel(0x000005f3, &mctl_phy->pir);
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udelay(10);
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mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
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if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
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*bus_width = 8;
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writel(0, &mctl_phy->dx1gcr);
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writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
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writel(0x5f3, &mctl_phy->pir);
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udelay(10000);
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setbits_le32(&mctl_ctl->mstr, 0x1000);
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} else
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*bus_width = 16;
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if (dram_para.odt_correction) {
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mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1,
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dram_para.odt_correction);
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mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1,
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dram_para.odt_correction);
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}
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mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
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writel(0x08003e3f, &mctl_phy->pgcr0);
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writel(0x00000000, &mctl_ctl->rfshctl3);
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}
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unsigned long sunxi_dram_init(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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const u32 columns = 13;
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u32 bus, bus_width, offset, page_size, rows;
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mctl_sys_init();
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mctl_init(&bus_width);
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if (bus_width == 16) {
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page_size = 8;
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bus = 1;
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} else {
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page_size = 7;
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bus = 0;
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}
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if (!(dram_para.tpr13 & 0x80000000)) {
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/* Detect and set rows */
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writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
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&mctl_com->cr);
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setbits_le32(&mctl_com->swonr, 0x0003ffff);
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for (rows = 11; rows < 16; rows++) {
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offset = 1 << (rows + columns + bus);
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if (mctl_mem_matches(offset))
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break;
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}
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clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
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MCTL_CR_ROW(rows));
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} else {
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rows = (dram_para.para1 >> 16) & 0xff;
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writel(((dram_para.para2 & 0x000000f0) << 11) |
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((rows - 1) << 4) |
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((dram_para.para1 & 0x0f000000) >> 22) |
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0x31000 | MCTL_CR_PAGE_SIZE(page_size),
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&mctl_com->cr);
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setbits_le32(&mctl_com->swonr, 0x0003ffff);
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}
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/* Setup DRAM master priority? If this is left out things still work */
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writel(0x00000008, &mctl_com->mcr0_0);
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writel(0x0001000d, &mctl_com->mcr1_0);
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writel(0x00000004, &mctl_com->mcr0_1);
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writel(0x00000080, &mctl_com->mcr1_1);
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writel(0x00000004, &mctl_com->mcr0_2);
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writel(0x00000019, &mctl_com->mcr1_2);
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writel(0x00000004, &mctl_com->mcr0_3);
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writel(0x00000080, &mctl_com->mcr1_3);
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writel(0x00000004, &mctl_com->mcr0_4);
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writel(0x01010040, &mctl_com->mcr1_4);
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writel(0x00000004, &mctl_com->mcr0_5);
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writel(0x0001002f, &mctl_com->mcr1_5);
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writel(0x00000004, &mctl_com->mcr0_6);
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writel(0x00010020, &mctl_com->mcr1_6);
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writel(0x00000004, &mctl_com->mcr0_7);
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writel(0x00010020, &mctl_com->mcr1_7);
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writel(0x00000008, &mctl_com->mcr0_8);
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writel(0x00000001, &mctl_com->mcr1_8);
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writel(0x00000008, &mctl_com->mcr0_9);
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writel(0x00000005, &mctl_com->mcr1_9);
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writel(0x00000008, &mctl_com->mcr0_10);
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writel(0x00000003, &mctl_com->mcr1_10);
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writel(0x00000008, &mctl_com->mcr0_11);
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writel(0x00000005, &mctl_com->mcr1_11);
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writel(0x00000008, &mctl_com->mcr0_12);
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writel(0x00000003, &mctl_com->mcr1_12);
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writel(0x00000008, &mctl_com->mcr0_13);
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writel(0x00000004, &mctl_com->mcr1_13);
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writel(0x00000008, &mctl_com->mcr0_14);
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writel(0x00000002, &mctl_com->mcr1_14);
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writel(0x00000008, &mctl_com->mcr0_15);
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writel(0x00000003, &mctl_com->mcr1_15);
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writel(0x00010138, &mctl_com->bwcr);
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return 1 << (rows + columns + bus);
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}
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