00b1883a4c
rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
#ifndef __CONFIG_H
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#define __CONFIG_H
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#undef DEBUG
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#define CONFIG_SH 1
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#define CONFIG_SH4 1
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#define CONFIG_CPU_SH7751 1
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#define CONFIG_CPU_SH_TYPE_R 1
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#define CONFIG_R2DPLUS 1
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#define __LITTLE_ENDIAN__ 1
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DFL
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_EXT2
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#define CONFIG_DOS_PARTITION
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_CONS_SCIF1 1
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#define BOARD_LATE_INIT 1
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#define CONFIG_BOOTDELAY -1
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#define CONFIG_BOOTARGS "console=ttySC0,115200"
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#define CONFIG_ENV_OVERWRITE 1
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/* SDRAM */
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#define CFG_SDRAM_BASE (0x8C000000)
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#define CFG_SDRAM_SIZE (0x04000000)
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#define CFG_LONGHELP
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#define CFG_PROMPT "=> "
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#define CFG_CBSIZE 256
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#define CFG_PBSIZE 256
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#define CFG_MAXARGS 16
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#define CFG_BARGSIZE 512
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/* List of legal baudrate settings for this board */
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#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
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#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
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#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
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#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
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/* Address of u-boot image in Flash */
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
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#define CFG_MONITOR_LEN (256 * 1024)
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/* Size of DRAM reserved for malloc() use */
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#define CFG_MALLOC_LEN (1024 * 1024)
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/* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_SIZE (256)
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#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
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/*
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* NOR Flash ( Spantion S29GL256P )
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*/
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#define CFG_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CFG_FLASH_BASE (0xA0000000)
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#define CFG_MAX_FLASH_BANKS (1)
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#define CFG_MAX_FLASH_SECT 256
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x40000
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#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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/*
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* SuperH Clock setting
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*/
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#define CONFIG_SYS_CLK_FREQ 60000000
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#define TMU_CLK_DIVIDER 4
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#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
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#define CFG_PLL_SETTLING_TIME 100/* in us */
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/*
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* IDE support
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*/
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#define CONFIG_IDE_RESET 1
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#define CFG_PIO_MODE 1
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#define CFG_IDE_MAXBUS 1 /* IDE bus */
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#define CFG_IDE_MAXDEVICE 1
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#define CFG_ATA_BASE_ADDR 0xb4000000
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#define CFG_ATA_STRIDE 2 /* 1bit shift */
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#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
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#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
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#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
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/*
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* SuperH PCI Bridge Configration
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*/
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#define CONFIG_PCI
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#define CONFIG_SH4_PCI
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#define CONFIG_SH7751_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW 1
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#define __io
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#define __mem_pci
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#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
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#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
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/*
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* Network device (RTL8139) support
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_RTL8139
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#define _IO_BASE 0x00000000
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#define KSEG1ADDR(x) (x)
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#endif /* __CONFIG_H */
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