240 lines
6.9 KiB
C
240 lines
6.9 KiB
C
/*
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* Configuation settings for the Motorola MC5272C3 board.
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*
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* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _M5272C3_H
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#define _M5272C3_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MCF52x2 /* define processor family */
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#define CONFIG_M5272 /* define processor type */
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#define CONFIG_MCFTMR
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#define CONFIG_MCFUART
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#define CFG_UART_PORT (0)
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#undef CONFIG_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
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#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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#define CFG_ENV_OFFSET 0x4000
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#define CFG_ENV_SECT_SIZE 0x2000
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_IS_EMBEDDED 1
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#else
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#define CFG_ENV_ADDR 0xffe04000
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#define CFG_ENV_SECT_SIZE 0x2000
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#define CFG_ENV_IS_IN_FLASH 1
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_MEMORY
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_LOADB
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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# define CONFIG_NET_MULTI 1
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# define CONFIG_MII 1
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# define CONFIG_MII_INIT 1
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# define CFG_DISCOVER_PHY
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# define CFG_RX_ETH_BUFFER 8
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# define CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FEC0_PINMUX 0
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# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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/* If CFG_DISCOVER_PHY is not defined - hardcoded */
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# ifndef CFG_DISCOVER_PHY
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# define FECDUPLEX FULL
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# define FECSPEED _100BASET
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# else
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# ifndef CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FAULT_ECHO_LINK_DOWN
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# endif
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# endif /* CFG_DISCOVER_PHY */
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#endif
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#ifdef CONFIG_MCFFEC
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_GATEWAYIP 192.162.1.1
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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#endif /* CONFIG_MCFFEC */
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#define CONFIG_HOSTNAME M5272C3
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=10000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off ffe00000 ffe3ffff;" \
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"era ffe00000 ffe3ffff;" \
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"cp.b ${loadaddr} ffe00000 ${filesize};"\
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"save\0" \
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""
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#define CFG_PROMPT "-> "
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#define CFG_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x20000
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#define CFG_MEMTEST_START 0x400
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#define CFG_MEMTEST_END 0x380000
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#define CFG_HZ 1000
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#define CFG_CLK 66000000
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CFG_MBAR 0x10000000 /* Register Base Addrs */
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#define CFG_SCR 0x0003;
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#define CFG_SPR 0xffff;
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR 0x20000000
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
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#define CFG_FLASH_BASE 0xffe00000
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#ifdef CONFIG_MONITOR_IS_IN_RAM
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#define CFG_MONITOR_BASE 0x20000
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#else
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
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#endif
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#define CFG_MONITOR_LEN 0x20000
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#define CFG_MALLOC_LEN (256 << 10)
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#define CFG_BOOTPARAMS_LEN 64*1024
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 1000
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16
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/*-----------------------------------------------------------------------
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* Memory bank definitions
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*/
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#define CFG_BR0_PRELIM 0xFFE00201
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#define CFG_OR0_PRELIM 0xFFE00014
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#define CFG_BR1_PRELIM 0
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#define CFG_OR1_PRELIM 0
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#define CFG_BR2_PRELIM 0x30000001
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#define CFG_OR2_PRELIM 0xFFF80000
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#define CFG_BR3_PRELIM 0
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#define CFG_OR3_PRELIM 0
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#define CFG_BR4_PRELIM 0
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#define CFG_OR4_PRELIM 0
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#define CFG_BR5_PRELIM 0
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#define CFG_OR5_PRELIM 0
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#define CFG_BR6_PRELIM 0
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#define CFG_OR6_PRELIM 0
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#define CFG_BR7_PRELIM 0x00000701
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#define CFG_OR7_PRELIM 0xFFC0007C
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/*-----------------------------------------------------------------------
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* Port configuration
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*/
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#define CFG_PACNT 0x00000000
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#define CFG_PADDR 0x0000
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#define CFG_PADAT 0x0000
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#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
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#define CFG_PBDDR 0x0000
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#define CFG_PBDAT 0x0000
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#define CFG_PDCNT 0x00000000
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#endif /* _M5272C3_H */
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