c99512d6bd
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
354 lines
9.8 KiB
C
354 lines
9.8 KiB
C
/*
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* (C) Copyright 2003-2006
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
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#define CONFIG_UC101 1 /* UC101 board */
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#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CONFIG_BOARD_EARLY_INIT_R
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/* Partitions */
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#define CONFIG_DOS_PARTITION
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/*
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* Supported commands
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*/
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_DATE | \
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CFG_CMD_DISPLAY | \
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CFG_CMD_DHCP | \
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CFG_CMD_PING | \
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CFG_CMD_EEPROM | \
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CFG_CMD_I2C | \
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CFG_CMD_DTT | \
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CFG_CMD_IDE | \
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CFG_CMD_FAT | \
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CFG_CMD_NFS | \
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CFG_CMD_MII | \
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CFG_CMD_SNTP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
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#if (TEXT_BASE == 0xFFF00000) /* Boot low */
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# define CFG_LOWBOOT 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addwdt=setenv bootargs ${bootargs} wdt=off" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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#define CONFIG_MISC_INIT_R 1
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/*
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* IPB Bus clocking configuration.
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*/
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#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CFG_I2C_SPEED 100000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CFG_I2C_EEPROM_ADDR 0x58
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* for LM81 */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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/*
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* RTC configuration
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*/
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#define CONFIG_RTC_PCF8563
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#define CFG_I2C_RTC_ADDR 0x51
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/* I2C SYSMON (LM75) */
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#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CFG_DTT_MAX_TEMP 70
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#define CFG_DTT_LOW_TEMP -30
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#define CFG_DTT_HYSTERESIS 3
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/*
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* Flash configuration
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*/
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#define CFG_FLASH_BASE 0xFF800000
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#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
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#define CFG_MAX_FLASH_SECT 140 /* max num of sects on one chip */
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#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
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#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
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(= chip selects) */
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_CFI
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_FLASH_CFI_AMD_RESET
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/*
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* Environment settings
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 0x4000
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#define CFG_ENV_SECT_SIZE 0x10000
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*
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* Memory map
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*/
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#define CFG_MBAR 0xF0000000
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#define CFG_DEFAULT_MBAR 0x80000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SRAM_BASE 0x80100000 /* CS 1 */
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#define CFG_DISPLAY_BASE 0x80600000 /* CS 3 */
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#define CFG_IB_MASTER 0xc0510000 /* CS 6 */
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#define CFG_IB_EPLD 0xc0500000 /* CS 7 */
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/* Settings for XLB = 132 MHz */
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#define SDRAM_DDR 1
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x714f0f00
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#define SDRAM_CONFIG1 0x73722930
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#define SDRAM_CONFIG2 0x47770000
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#define SDRAM_TAPDELAY 0x10000000
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/* SRAM */
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#define SRAM_BASE CFG_SRAM_BASE /* SRAM base address */
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#define SRAM_LEN 0x1fffff
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#define SRAM_END (SRAM_BASE + SRAM_LEN)
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/* Use ON-Chip SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
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#else
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
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#endif
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT 1
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#endif
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_PHY_ADDR 0x00
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#define CONFIG_MII 1
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/*
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* GPIO configuration
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*/
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#define CFG_GPS_PORT_CONFIG 0x4d558044
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/*use Hardware WDT */
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#define CONFIG_HW_WATCHDOG
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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/* Enable an alternate, more extensive memory test */
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#define CFG_ALT_MEMTEST
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#define CFG_MEMTEST_START 0x00300000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x300000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*
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* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
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* which is normally part of the default commands (CFV_CMD_DFL)
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*/
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#define CONFIG_LOOPW
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/*
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* Various low-level settings
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*/
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#if defined(CONFIG_MPC5200)
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#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
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#define CFG_HID0_FINAL HID0_ICE
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#else
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL 0
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#endif
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#define CFG_BOOTCS_START CFG_FLASH_BASE
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#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
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#define CFG_BOOTCS_CFG 0x00045D00
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#define CFG_CS0_START CFG_FLASH_BASE
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#define CFG_CS0_SIZE CFG_FLASH_SIZE
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/* 8Mbit SRAM @0x80100000 */
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#define CFG_CS1_START CFG_SRAM_BASE
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#define CFG_CS1_SIZE 0x00100000
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#define CFG_CS1_CFG 0x21D00
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/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
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#define CFG_CS3_START CFG_DISPLAY_BASE
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#define CFG_CS3_SIZE 0x00000100
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#define CFG_CS3_CFG 0x00081802
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/* Interbus Master 16 Bit */
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#define CFG_CS6_START CFG_IB_MASTER
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#define CFG_CS6_SIZE 0x00010000
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#define CFG_CS6_CFG 0x00FF3500
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/* Interbus EPLD 8 Bit */
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#define CFG_CS7_START CFG_IB_EPLD
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#define CFG_CS7_SIZE 0x00010000
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#define CFG_CS7_CFG 0x00081800
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x33333333
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
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#define CONFIG_IDE_PREINIT 1
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/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CFG_ATA_STRIDE 4
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#define CONFIG_ATAPI 1
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/*---------------------------------------------------------------------*/
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/* Display addresses */
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/*---------------------------------------------------------------------*/
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#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
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#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
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#endif /* __CONFIG_H */
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