8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
203 lines
8.4 KiB
Plaintext
203 lines
8.4 KiB
Plaintext
PowerPC 440
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Last Update: September 11, 2002
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=======================================================================
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OVERVIEW
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============
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Support for the ppc440 is contained in the cpu/ppc44x directory
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and enabled via the CONFIG_440 flag. It is largely based on the
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405gp code. A sample board support implementation is contained
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in the board/ebony directory.
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All testing was performed using the IBM Ebony board using both
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Rev B and Rev C silicon. However, since the Rev B. silicon has
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extensive errata, support for Rev B. is minimal (it boots, and
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features such as i2c, pci, tftpboot, etc. seem to work ok).
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The expectation is that all new board designs will be using
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Rev C or later parts -- if not, you may be in for a rough ride ;-)
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The ppc440 port does a fair job of keeping "board-specific" code
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out of the "cpu-specific" source. The goal of course was to
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provide mechanisms for each board to customize without having
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to clutter the cpu-specific source with a lot of ifdefs. Most
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of these mechanisms are described in the following sections.
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MEMORY MANAGEMENT
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=================
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The ppc440 doesn't run in "real mode". The MMU must be active
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at all times. Additionally, the 440 implements a 36-bit physical
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memory space that gets mapped into the PowerPC 32-bit virtual
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address space. So things like memory-mapped peripherals, etc must
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all be mapped in. Once this is done, the 32-bit virtual address
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space is then viewed as though it were physical memory.
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However, this means that memory, peripherals, etc can be configured
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to appear (mostly) anywhere in the virtual address space. Each board
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must define its own mappings using the tlbtab (see board/ebony/init.S).
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The actual TLB setup is performed by the cpu-specific code.
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Although each board is free to define its own mappings, there are
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several definitions to be aware of. These definitions may be used in
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the cpu-specific code (vs. board-specific code), so you should
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at least review these before deciding to make any changes ... it
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will probably save you some headaches ;-)
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CFG_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0)
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CFG_FLASH_BASE - The virtual address where FLASH is mapped.
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CFG_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped.
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This mapping provides access to PCI-bus memory.
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CFG_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped
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peripherals are mapped. (e.g. -- UART registers, IIC registers, etc).
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CFG_ISRAM_BASE - The virtual address where the 440 internal SRAM is
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mapped. The internal SRAM is equivalent to 405gp OCM and is used
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for the initial stack.
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CFG_PCI_BASE - The virtual address where the 440 PCI-x bridge config
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registers are mapped.
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CFG_PCI_TARGBASE - The PCI address that is mapped to the virtual address
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defined by CFG_PCI_MEMBASE.
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UART / SERIAL
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=================
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The UART port works fine when an external serial clock is provided
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(like the one on the Ebony board) and when using internal clocking.
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This is controlled with the CFG_EXT_SERIAL_CLOCK flag. When using
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internal clocking, the "ideal baud rate" settings in the 440GP
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user manual are automatically calculated.
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CONFIG_SERIAL_SOFTWARE_FIFO enables interrupt-driven serial operation.
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But the last time I checked, interrupts were initialized after the
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serial port causing the interrupt handler to be removed from the
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handler table. This will probably be fixed soon ... or fix it
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yourself and submit a patch :-)
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I2C
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=================
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The i2c utilities have been tested on both Rev B. and Rev C. and
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look good. The iprobe command implementation has been updated to
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allow for 'skipped' addresses. Some i2c slaves are write only and
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cause problems when a probe (read) is performed (for example the
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CDCV850 clock controller at address 0x69 on the ebony board).
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To prevent probing certain addresses you can define the
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CFG_I2C_NOPROBES macro in your board-specific header file. When
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defined, all specified addresses are skipped during a probe.
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The addresses that are skipped will be displayed in the output
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of the iprobe command.
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For example, to prevent probing address 0x69, define the macro as
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follows:
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#define CFG_I2C_NOPROBES {0x69}
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Similarly, to prevent probing addresses 0x69 and 0x70, define the
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macro a:
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#define CFG_I2C_NOPROBES {0x69, 0x70}
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DDR SDRAM CONTROLLER
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====================
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SDRAM controller intialization using Serial Presence Detect (SPD) is
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now supported (thanks Jun). It is enabled by defining CONFIG_SPD_EEPROM.
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The i2c eeprom addresses are controlled by the SPD_EEPROM_ADDRESS macro.
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NOTE: The SPD_EEPROM_ADDRESS macro is defined differently than for other
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processors. Traditionally, it defined a single address. For the 440 it
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defines an array of addresses to support multiple banks. Address order
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is significant: the addresses are used in order to program the BankN
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registers. For example, two banks with i2c addresses of 0x53 (bank 0)
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and 0x52 (bank 1) would be defined as follows:
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#define SPD_EEPROM_ADDRESS {0x53,0x52}
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PCI-X BRIDGE
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====================
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PCI is an area that requires lots of flexibility since every board has
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its own set of constraints and configuration. This section describes the
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440 implementation.
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CPC0_STRP1[PISE] -- if the PISE strap bit is not asserted, PCI init
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is aborted and an indication is printed. This is NOT considered an
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error -- only an indication that PCI shouldn't be initialized. This
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gives you a chance to edit the i2c bootstrap eeproms using the i2c
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utilities once you get to the U-Boot command prompt. NOTE: the default
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440 bootstrap options (not using i2c eeprom) negates this bit.
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The cpu-specific code sets up a default pci_controller structure
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that maps in a single PCI I/O space and PCI memory space. The I/O
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space begins at PCI I/O address 0 and the PCI memory space is
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256 MB starting at PCI address CFG_PCI_TARGBASE. After the
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pci_controller structure is initialized, the cpu-specific code will
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call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is
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defined. This routine is implemented by board-specific code & is where
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the board can over-ride/extend the default pci_controller structure
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settings and do other pre-initialization tasks. If pci_pre_init()
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returns a value of zero, PCI initialization is aborted; otherwise the
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controller structure is registered and initialization continues.
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The default 440GP PCI target configuration is minimal -- it assumes that
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the strapping registers are set as necessary. Since the strapping bits
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provide very limited flexibility, you may want to customize the boards
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target configuration. If CFG_PCI_TARGET_INIT is defined, the cpu-specific
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code will call the routine pci_target_init() which you must implement
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in your board-specific code.
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Target initialization is completed by the cpu-specific code by
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initializing the subsystem id and subsystem vendor id, and then ensuring
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that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set.
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The default PCI master initialization maps in 256 MB of pci memory
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starting at PCI address CFG_PCI_MEMBASE. To customize this, define
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PCI_MASTER_INIT. This will call the routine pci_master_init() in your
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board-specific code rather than performing the default master
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initialization.
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The decision to perform PCI host configuration must often be determined
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at run time. The ppc440 port differs from most other implementations in
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that it requires the board to determine its host configuration at run
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time rather than by using compile-time flags. This shouldn't create a
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large impact on the board-specific code since the board only needs to
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implement a single routine that returns a zero or non-zero value:
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is_pci_host().
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Justification for this becomes clear when considering systems running
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in a cPCI environment:
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1. Arbiter strapping: Many cPCI boards provide an external arbiter (often
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part of the PCI-to-PCI bridge). Even though the arbiter is external (the
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arbiter strapping is negated), the CPU may still be required to perform
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local PCI bus configuration.
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2. Host only: PPMC boards must sample the MONARCH# signal at run-time.
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Depending on the configuration of the carrier boar, the PPMC board must
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determine if it should configure the PCI bus at run-time. And in most
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cases, access to the MONARCH# signal is board-specific (e.g. via
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board-specific FPGA registers, etc).
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In any event, the is_pci_host() routine gives each board the opportunity
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to decide at run-time. If your board is always configured a certain way,
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then just hardcode a return of 1 or 0 as appropriate.
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Regards,
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--Scott
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<smcnutt@artesyncp.com>
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