162 lines
4.1 KiB
C
162 lines
4.1 KiB
C
/*
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* (C) Copyright 2008
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* Based on board/amcc/yosemite/yosemite.c
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/4xx_pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* info for FLASH chips */
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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int board_early_init_f(void)
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{
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register uint reg;
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/*
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* Setup the external bus controller/chip selects
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*/
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mfebc(EBC0_CFG, reg);
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mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */
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/*
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* Setup the GPIO pins
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*/
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/* setup Address lines for flash size 64Meg. */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
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/* setup emac */
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
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out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
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/* UART0 and UART1*/
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000);
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000);
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out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
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out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
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/* disable boot-eeprom WP */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
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out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
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/* external interrupts IRQ0...3 */
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out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
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out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
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out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
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mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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/*
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* Setup other serial configuration
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*/
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mfsdr(SDR0_PCI0, reg);
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mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
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mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
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mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
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return 0;
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}
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int misc_init_r(void)
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{
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uint pbcr;
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int size_val;
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uint sz;
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/* Re-do sizing to get full correct info */
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mfebc(PB0CR, pbcr);
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if (gd->bd->bi_flashsize > 0x08000000)
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panic("Max. flash banksize is 128 MB!\n");
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for (sz = gd->bd->bi_flashsize, size_val = 7;
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((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
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sz <<= 1;
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtebc(PB0CR, pbcr);
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return 0;
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}
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/*
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* Override weak pci_pre_init()
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*/
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#if defined(CONFIG_PCI)
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int pci_pre_init(struct pci_controller *hose)
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{
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/* First call common code */
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__pci_pre_init(hose);
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/* enable 66 MHz ext. Clock */
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
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out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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