edf95bdedd
According to i.MX7ULP Reference Manual we should wait for WDOG unlock and reconfiguration to complete. Section "59.5.3 Configure Watchdog" provides the following example: DisableInterrupts; //disable global interrupt WDOG_CNT = 0xD928C520; //unlock watchdog while(WDOG_CS[ULK]==0); //wait until registers are unlocked WDOG_TOVAL = 256; //set timeout value WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) | WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1); while(WDOG_CS[RCS]==0); //wait until new configuration takes effect EnableInterrupts; //enable global interrupt Update U-Boot WDOG driver to align with i.MX7ULP reference manual. Use 32 bits accessing to CS register. According to RM, the bits in this register only can write once after unlock. So using 8 bits access will cause problem. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
114 lines
2.5 KiB
C
114 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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/*
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* MX7ULP WDOG Register Map
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*/
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struct wdog_regs {
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u32 cs;
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u32 cnt;
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u32 toval;
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u32 win;
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};
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#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
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#endif
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#define REFRESH_WORD0 0xA602 /* 1st refresh word */
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#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
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#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
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#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
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#define WDGCS_WDGE BIT(7)
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#define WDGCS_WDGUPDATE BIT(5)
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#define WDGCS_RCS BIT(10)
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#define WDGCS_ULK BIT(11)
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#define WDGCS_FLG BIT(14)
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#define WDG_BUS_CLK (0x0)
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#define WDG_LPO_CLK (0x1)
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#define WDG_32KHZ_CLK (0x2)
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#define WDG_EXT_CLK (0x3)
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void hw_watchdog_set_timeout(u16 val)
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{
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/* setting timeout value */
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(val, &wdog->toval);
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}
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void hw_watchdog_reset(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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dmb();
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__raw_writel(REFRESH_WORD0, &wdog->cnt);
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__raw_writel(REFRESH_WORD1, &wdog->cnt);
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dmb();
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}
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void hw_watchdog_init(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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dmb();
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__raw_writel(UNLOCK_WORD0, &wdog->cnt);
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__raw_writel(UNLOCK_WORD1, &wdog->cnt);
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dmb();
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/* Wait WDOG Unlock */
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while (!(readl(&wdog->cs) & WDGCS_ULK))
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;
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hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
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writel(0, &wdog->win);
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/* setting 1-kHz clock source, enable counter running, and clear interrupt */
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writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);
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/* Wait WDOG reconfiguration */
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while (!(readl(&wdog->cs) & WDGCS_RCS))
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;
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hw_watchdog_reset();
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}
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void reset_cpu(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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dmb();
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__raw_writel(UNLOCK_WORD0, &wdog->cnt);
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__raw_writel(UNLOCK_WORD1, &wdog->cnt);
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dmb();
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/* Wait WDOG Unlock */
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while (!(readl(&wdog->cs) & WDGCS_ULK))
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;
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hw_watchdog_set_timeout(5); /* 5ms timeout */
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writel(0, &wdog->win);
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/* enable counter running */
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writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
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/* Wait WDOG reconfiguration */
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while (!(readl(&wdog->cs) & WDGCS_RCS))
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;
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hw_watchdog_reset();
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while (1);
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}
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