3281532ab2
I did not enable SDMA when I added sdhci-cadence support because LD20 boards are equipped with a large amount memory beyond 32 bit address range, but SDMA does not support the 64bit address. U-Boot relocates itself to the end of effectively available RAM. This would make the MMC enumeration fail because the buffer for EXT_CSD allocated in the stack would go too high, then SDMA would fail to transfer data. Recent SDHCI-compatible controllers support ADMA, but unfortunately U-Boot does not support ADMA. In the previous commit, I hided the DRAM area that exceeds the 32 bit address range. Now, I can enable CONFIG_MMC_SDHCI_SDMA. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
56 lines
1.3 KiB
Plaintext
56 lines
1.3 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARM_SMCCC=y
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CONFIG_ARCH_UNIPHIER=y
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CONFIG_SYS_TEXT_BASE=0x84000000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ARCH_UNIPHIER_V8_MULTI=y
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CONFIG_MICRO_SUPPORT_CARD=y
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CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_LOGLEVEL=6
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_CONFIG=y
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CONFIG_CMD_IMLS=y
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_ENV_EXISTS is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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# CONFIG_CMD_MISC is not set
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_GPIO_UNIPHIER=y
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CONFIG_MISC=y
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CONFIG_I2C_EEPROM=y
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
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CONFIG_MMC_UNIPHIER=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_CADENCE=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_NAND=y
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CONFIG_NAND_DENALI_DT=y
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CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
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CONFIG_NETDEVICES=y
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CONFIG_SMC911X=y
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CONFIG_SMC911X_BASE=0x0
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CONFIG_SMC911X_32_BIT=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET_PSCI=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_UNIPHIER=y
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CONFIG_USB_STORAGE=y
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CONFIG_PANIC_HANG=y
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