689 lines
22 KiB
C
689 lines
22 KiB
C
/*
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* (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
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* Stephan Linz <linz@li-pro.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/***********************************************************************
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* Include the whole NIOS CPU configuration.
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*
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* !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
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*
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***********************************************************************/
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#if defined(CONFIG_NIOS_BASE_32)
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#include <configs/ADNPESC1_base_32.h>
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#else
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#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
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#endif
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/*------------------------------------------------------------------------
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* BOARD/CPU -- TOP-LEVEL
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*----------------------------------------------------------------------*/
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#define CONFIG_NIOS 1 /* NIOS-32 core */
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#define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */
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#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
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#define CFG_HZ 1000 /* 1 msec time tick */
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#undef CFG_CLKS_IN_HZ
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
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/*------------------------------------------------------------------------
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* BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
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#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
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#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
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#else
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#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
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#endif
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#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
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#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
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#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
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#else
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#undef CFG_SRAM_BASE
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#undef CFG_SRAM_SIZE
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#endif
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#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
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/*------------------------------------------------------------------------
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* MEMORY ORGANIZATION - For the most part, you can put things pretty
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* much anywhere. This is pretty flexible for Nios. So here we make some
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* arbitrary choices & assume that the monitor is placed at the end of
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* a memory resource (so you must make sure TEXT_BASE is chosen
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* appropriately -- this is very important if you plan to move your
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* memory to another place as configured at this time !!!).
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*
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* -The heap is placed below the monitor.
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* -Global data is placed below the heap.
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* -The stack is placed below global data (&grows down).
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
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#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
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#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
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/*------------------------------------------------------------------------
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* FLASH (AM29LV065D)
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
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#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
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#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
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#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
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#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
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#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
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#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
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#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size */
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#else
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#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
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#endif
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/*------------------------------------------------------------------------
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* ENVIRONMENT
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
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#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
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/* Mem addr of environment */
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#if defined(CONFIG_NIOS_BASE_32)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
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#else
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#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
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#endif
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#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
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#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
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#else
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#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
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#endif
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/*------------------------------------------------------------------------
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* NIOS APPLICATION CODE BASE AREA
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*----------------------------------------------------------------------*/
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#if ((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000)
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#define CFG_ADNPESC1_UPDATE_LOAD_ADDR "0x2000100"
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#define CFG_ADNPESC1_NIOS_APPL_ENTRY "0x1050000"
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#define CFG_ADNPESC1_NIOS_APPL_IDENT "0x105000c"
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#define CFG_ADNPESC1_NIOS_APPL_END "0x11fffff"
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#define CFG_ADNPESC1_FILESYSTEM_BASE "0x1200000"
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#define CFG_ADNPESC1_FILESYSTEM_END "0x17fffff"
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#else
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#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
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#endif
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#define CFG_ADNPESC1_NIOS_IDENTIFIER "Nios"
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/*------------------------------------------------------------------------
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* BOOT ENVIRONMENT
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*----------------------------------------------------------------------*/
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#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
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#define CFG_ADNPESC1_SLED_BOOT_OFF "sled boot off; "
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#define CFG_ADNPESC1_SLED_RED_BLINK "sled red blink; "
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#else
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#define CFG_ADNPESC1_SLED_BOOT_OFF
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#define CFG_ADNPESC1_SLED_RED_BLINK
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#endif
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOTCOMMAND \
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"if itest.s *$appl_ident_addr == \"$appl_ident_str\"; " \
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"then " \
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"wd off; " \
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CFG_ADNPESC1_SLED_BOOT_OFF \
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"go $appl_entry_addr; " \
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"else " \
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CFG_ADNPESC1_SLED_RED_BLINK \
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"echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
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"echo *** invalid application at $appl_entry_addr; " \
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"echo *** stop bootup...; " \
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"fi"
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/*------------------------------------------------------------------------
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* EXTRA ENVIRONMENT
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*----------------------------------------------------------------------*/
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#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
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#define CFG_ADNPESC1_SLED_YELLO_ON "sled yellow on; "
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#define CFG_ADNPESC1_SLED_YELLO_OFF "sled yellow off; "
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#else
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#define CFG_ADNPESC1_SLED_YELLO_ON
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#define CFG_ADNPESC1_SLED_YELLO_OFF
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"update_allowed=0\0" \
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"update_load_addr=" CFG_ADNPESC1_UPDATE_LOAD_ADDR "\0" \
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"appl_entry_addr=" CFG_ADNPESC1_NIOS_APPL_ENTRY "\0" \
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"appl_end_addr=" CFG_ADNPESC1_NIOS_APPL_END "\0" \
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"appl_ident_addr=" CFG_ADNPESC1_NIOS_APPL_IDENT "\0" \
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"appl_ident_str=" CFG_ADNPESC1_NIOS_IDENTIFIER "\0" \
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"appl_name=ADNPESC1/base32/linux.bin\0" \
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"appl_update=" \
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"if itest.b $update_allowed != 0; " \
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"then " \
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CFG_ADNPESC1_SLED_YELLO_ON \
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"tftp $update_load_addr $appl_name; " \
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"protect off $appl_entry_addr $appl_end_addr; " \
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"era $appl_entry_addr $appl_end_addr; " \
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"cp.b $update_load_addr $appl_entry_addr $filesize; "\
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CFG_ADNPESC1_SLED_YELLO_OFF \
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"else " \
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"echo *** update not allowed (update_allowed=$update_allowed); "\
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"fi\0" \
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"fs_base_addr=" CFG_ADNPESC1_FILESYSTEM_BASE "\0" \
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"fs_end_addr=" CFG_ADNPESC1_FILESYSTEM_END "\0" \
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"fs_name=ADNPESC1/base32/romfs.img\0" \
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"fs_update=" \
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"if itest.b $update_allowed != 0; " \
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"then " \
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CFG_ADNPESC1_SLED_YELLO_ON \
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"tftp $update_load_addr $fs_name; " \
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"protect off $fs_base_addr $fs_end_addr; " \
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"era $fs_base_addr $fs_end_addr; " \
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"cp.b $update_load_addr $fs_base_addr $filesize; "\
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CFG_ADNPESC1_SLED_YELLO_OFF \
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"else " \
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"echo *** update not allowed (update_allowed=$update_allowed); "\
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"fi\0" \
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"uboot_name=ADNPESC1/base32/u-boot.bin\0" \
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"uboot_loadnrun=" \
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"if ping $serverip; " \
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"then " \
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CFG_ADNPESC1_SLED_YELLO_ON \
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"tftp $update_load_addr $uboot_name; " \
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"wd off; " \
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"go $update_load_addr; " \
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"else " \
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"echo *** missing connection to $serverip; " \
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"echo *** check your network and try again...; "\
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"fi\0"
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/*------------------------------------------------------------------------
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* CONSOLE
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_UART_NUMS != 0)
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#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
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#if (CFG_NIOS_CPU_UART0_BR != 0)
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#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
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#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
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#else
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#undef CFG_NIOS_FIXEDBAUD
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#define CONFIG_BAUDRATE 115200
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#endif
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#else
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#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
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#endif
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/*------------------------------------------------------------------------
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* TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
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* so an avalon bus timer is required.
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
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#if (CFG_NIOS_CPU_TICK_TIMER == 0)
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#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
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#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
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#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */
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#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
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#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
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#else
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#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
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#endif
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#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
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#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */
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#if (CFG_HZ <= 1000)
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#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
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#else
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#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
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#endif
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#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
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#else
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#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
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#endif
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#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
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#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
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#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
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#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */
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#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
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#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
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#else
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#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
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#endif
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#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
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#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */
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#if (CFG_HZ <= 1000)
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#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
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#else
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#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
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#endif
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#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
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#else
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#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
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#endif
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#endif /* CFG_NIOS_CPU_TICK_TIMER */
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#else
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#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
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#endif
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/*------------------------------------------------------------------------
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* WATCHDOG (or better MAX823 supervisory circuite access)
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*----------------------------------------------------------------------*/
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#define CONFIG_HW_WATCHDOG 1 /* board specific WD */
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#ifdef CONFIG_HW_WATCHDOG
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/* MAX823 supervisor -- watchdog enable port at: */
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#if (CFG_NIOS_CPU_WDENA_PIO == 0)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 1)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 2)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 3)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 4)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 5)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 6)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 7)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 8)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */
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#elif (CFG_NIOS_CPU_WDENA_PIO == 9)
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#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */
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#else
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#error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
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#endif
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/* MAX823 supervisor -- watchdog trigger port at: */
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#if (CFG_NIOS_CPU_WDTOG_PIO == 0)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 1)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 2)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 3)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 4)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 5)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 6)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 7)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 8)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */
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#elif (CFG_NIOS_CPU_WDTOG_PIO == 9)
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#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */
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#else
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#error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
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#endif
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#if defined(CONFIG_NIOS_BASE_32) /* NIOS CPU specifics */
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#define CONFIG_HW_WDENA_BIT 0 /* WD enable @ Bit 0 */
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#define CONFIG_HW_WDTOG_BIT 0 /* WD trigger @ Bit 0 */
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#define CONFIG_HW_WDPORT_WRONLY 1 /* each WD port wr/only*/
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#else
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#error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h
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#endif
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#endif /* CONFIG_HW_WATCHDOG */
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/*------------------------------------------------------------------------
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* SERIAL PERIPHAREL INTERFACE
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_SPI_NUMS == 1)
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#define CONFIG_NIOS_SPI 1 /* SPI support active */
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#define CFG_NIOS_SPIBASE CFG_NIOS_CPU_SPI0
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#define CFG_NIOS_SPIBITS CFG_NIOS_CPU_SPI0_BITS
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#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */
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#define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */
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#else
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#undef CONFIG_NIOS_SPI /* NO SPI support */
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#endif
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/*------------------------------------------------------------------------
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* Ethernet -- needs work!
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_LAN_NUMS == 1)
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#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
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#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
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#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
|
|
#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
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|
|
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#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
|
|
#define CONFIG_SMC_USE_32_BIT 1
|
|
#else /* no */
|
|
#undef CONFIG_SMC_USE_32_BIT
|
|
#endif
|
|
|
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#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
|
|
|
|
/********************************************/
|
|
/* !!! CS8900 is __not__ tested on NIOS !!! */
|
|
/********************************************/
|
|
#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
|
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#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
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|
|
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#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
|
|
#undef CS8900_BUS16
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|
#define CS8900_BUS32 1
|
|
#else /* no */
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|
#define CS8900_BUS16 1
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|
#undef CS8900_BUS32
|
|
#endif
|
|
|
|
#else
|
|
#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
|
|
#endif
|
|
|
|
#define CONFIG_ETHADDR 02:80:ae:20:60:6f
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|
#define CONFIG_NETMASK 255.255.255.248
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|
#define CONFIG_IPADDR 192.168.161.84
|
|
#define CONFIG_SERVERIP 192.168.161.85
|
|
|
|
#else
|
|
#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
|
|
#endif
|
|
|
|
/*------------------------------------------------------------------------
|
|
* STATUS LEDs
|
|
*----------------------------------------------------------------------*/
|
|
#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
|
|
|
|
#if (CFG_NIOS_CPU_LED_PIO == 0)
|
|
|
|
#define STATUS_LED_BASE CFG_NIOS_CPU_PIO0
|
|
#define STATUS_LED_BITS CFG_NIOS_CPU_PIO0_BITS
|
|
#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
|
|
|
#if (CFG_NIOS_CPU_PIO0_TYPE == 1)
|
|
#define STATUS_LED_WRONLY 1
|
|
#else
|
|
#undef STATUS_LED_WRONLY
|
|
#endif
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 1)
|
|
|
|
#define STATUS_LED_BASE CFG_NIOS_CPU_PIO1
|
|
#define STATUS_LED_BITS CFG_NIOS_CPU_PIO1_BITS
|
|
#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
|
|
|
#if (CFG_NIOS_CPU_PIO1_TYPE == 1)
|
|
#define STATUS_LED_WRONLY 1
|
|
#else
|
|
#undef STATUS_LED_WRONLY
|
|
#endif
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 2)
|
|
|
|
#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
|
|
#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
|
|
#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
|
|
|
#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
|
|
#define STATUS_LED_WRONLY 1
|
|
#else
|
|
#undef STATUS_LED_WRONLY
|
|
#endif
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 3)
|
|
|
|
#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 4)
|
|
|
|
#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 5)
|
|
|
|
#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 6)
|
|
|
|
#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 7)
|
|
|
|
#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 8)
|
|
|
|
#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
|
|
|
|
#elif (CFG_NIOS_CPU_LED_PIO == 9)
|
|
|
|
#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
|
|
|
|
#else
|
|
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
|
|
#endif
|
|
|
|
#define CONFIG_STATUS_LED 1 /* enable status led driver */
|
|
|
|
#define STATUS_LED_BIT (1 << 0) /* LED[0] */
|
|
#define STATUS_LED_STATE STATUS_LED_BLINKING
|
|
#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
|
|
#define STATUS_LED_PERIOD (CFG_HZ / 2) /* ca. 1 Hz */
|
|
#define STATUS_LED_BOOT 0 /* boot LED */
|
|
|
|
#if (STATUS_LED_BITS > 1)
|
|
#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
|
|
#define STATUS_LED_STATE1 STATUS_LED_OFF
|
|
#define STATUS_LED_PERIOD1 (CFG_HZ / 10) /* ca. 5 Hz */
|
|
#define STATUS_LED_RED 1 /* fail LED */
|
|
#endif
|
|
|
|
#if (STATUS_LED_BITS > 2)
|
|
#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
|
|
#define STATUS_LED_STATE2 STATUS_LED_OFF
|
|
#define STATUS_LED_PERIOD2 (CFG_HZ / 2) /* ca. 1 Hz */
|
|
#define STATUS_LED_YELLOW 2 /* info LED */
|
|
#endif
|
|
|
|
#if (STATUS_LED_BITS > 3)
|
|
#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
|
|
#define STATUS_LED_STATE3 STATUS_LED_OFF
|
|
#define STATUS_LED_PERIOD3 (CFG_HZ / 2) /* ca. 1 Hz */
|
|
#define STATUS_LED_GREEN 3 /* info LED */
|
|
#endif
|
|
|
|
#define STATUS_LED_PAR 1 /* makes status_led.h happy */
|
|
|
|
#endif /* CFG_NIOS_CPU_PIO_NUMS */
|
|
|
|
/*------------------------------------------------------------------------
|
|
* Diagnostics / Power On Self Tests
|
|
*----------------------------------------------------------------------*/
|
|
#define CONFIG_POST CFG_POST_RTC
|
|
#define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
|
|
|
/*
|
|
* BOOTP options
|
|
*/
|
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
#define CONFIG_BOOTP_BOOTPATH
|
|
#define CONFIG_BOOTP_GATEWAY
|
|
#define CONFIG_BOOTP_HOSTNAME
|
|
|
|
/*
|
|
* Command line configuration.
|
|
*/
|
|
#include <config_cmd_default.h>
|
|
|
|
#define CONFIG_CMD_BSP
|
|
#define CONFIG_CMD_CDP
|
|
#define CONFIG_CMD_DHCP
|
|
#define CONFIG_CMD_DIAG
|
|
#define CONFIG_CMD_DISPLAY
|
|
#define CONFIG_CMD_EXT2
|
|
#define CONFIG_CMD_IMMAP
|
|
#define CONFIG_CMD_IRQ
|
|
#define CONFIG_CMD_PING
|
|
#define CONFIG_CMD_PORTIO
|
|
#define CONFIG_CMD_REGINFO
|
|
#define CONFIG_CMD_REISER
|
|
#define CONFIG_CMD_SAVES
|
|
#define CONFIG_CMD_SDRAM
|
|
#define CONFIG_CMD_SNTP
|
|
|
|
#undef CONFIG_CMD_NFS
|
|
#undef CONFIG_CMD_XIMG
|
|
|
|
#if (CFG_NIOS_CPU_SPI_NUMS == 1)
|
|
#define CONFIG_CMD_DATE
|
|
#define CONFIG_CMD_SPI
|
|
#endif
|
|
|
|
/*------------------------------------------------------------------------
|
|
* KGDB
|
|
*----------------------------------------------------------------------*/
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 9600
|
|
#endif
|
|
|
|
/*------------------------------------------------------------------------
|
|
* MISC
|
|
*----------------------------------------------------------------------*/
|
|
#define CFG_LONGHELP /* undef to save memory */
|
|
#define CFG_HUSH_PARSER 1 /* use "hush" command parser
|
|
undef to save memory */
|
|
#define CFG_PROMPT "ADNPESC1 > " /* Monitor Command Prompt */
|
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
|
#define CFG_MAXARGS 64 /* max number of command args*/
|
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
|
|
|
#ifdef CFG_HUSH_PARSER
|
|
#define CFG_PROMPT_HUSH_PS2 "[]> "
|
|
#endif
|
|
|
|
/* Default load address */
|
|
#if (CFG_SRAM_SIZE != 0)
|
|
|
|
/* default in SRAM */
|
|
#define CFG_LOAD_ADDR CFG_SRAM_BASE
|
|
|
|
#elif (CFG_SDRAM_SIZE != 0)
|
|
|
|
/* default in SDRAM */
|
|
#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
|
|
#if 1
|
|
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
|
|
#else
|
|
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x400000)
|
|
#endif
|
|
#else
|
|
#define CFG_LOAD_ADDR CFG_SDRAM_BASE
|
|
#endif
|
|
|
|
#else
|
|
#undef CFG_LOAD_ADDR /* force error break */
|
|
#endif
|
|
|
|
/* MEM test area */
|
|
#if (CFG_SDRAM_SIZE != 0)
|
|
|
|
/* SDRAM begin to stack area (1MB stack) */
|
|
#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
|
|
#if 0
|
|
#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
|
|
#else
|
|
#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x400000)
|
|
#endif
|
|
#else
|
|
#define CFG_MEMTEST_START CFG_SDRAM_BASE
|
|
#endif
|
|
|
|
#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
|
|
#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
|
|
|
|
#else
|
|
#undef CFG_MEMTEST_START /* force error break */
|
|
#undef CFG_MEMTEST_END
|
|
#endif
|
|
|
|
/*
|
|
* JFFS2 partitions
|
|
*
|
|
*/
|
|
/* No command line, one static partition */
|
|
#undef CONFIG_JFFS2_CMDLINE
|
|
#define CONFIG_JFFS2_DEV "nor"
|
|
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
|
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
|
|
|
/* mtdparts command line support */
|
|
/*
|
|
#define CONFIG_JFFS2_CMDLINE
|
|
#define MTDIDS_DEFAULT ""
|
|
#define MTDPARTS_DEFAULT ""
|
|
*/
|
|
|
|
#endif /* __CONFIG_H */
|