Wills Wang ca09e66b04 mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define ... Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip. Signed-off-by: Wills Wang <wills.wang@live.com>		2016-05-31 10:17:54 +02:00
..
cpu	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
dts	mips: ath79: ap121: Enable ethernet	2016-05-31 10:17:54 +02:00
include/asm	MIPS: Split I & D cache line size config	2016-05-31 09:44:24 +02:00
lib	MIPS: Abstract cache op loops with a macro	2016-05-31 09:44:24 +02:00
mach-ath79	mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define	2016-05-31 10:17:54 +02:00
mach-au1x00	MIPS: Kconfig: optimize gcc -march and -mtune setup	2016-01-16 21:06:46 +01:00
mach-pic32	board: Add Microchip PIC32MZ[DA]-Starter-Kit board.	2016-02-01 22:14:01 +01:00
config.mk	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
Kconfig	MIPS: Split I & D cache line size config	2016-05-31 09:44:24 +02:00
Makefile	MIPS: add tune for MIPS 34kc	2016-05-31 09:38:11 +02:00