a6d7e8c914
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
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ag101p_timer.c | ||
altera_timer.c | ||
andes_plmt_timer.c | ||
arc_timer.c | ||
ast_timer.c | ||
atcpit100_timer.c | ||
atmel_pit_timer.c | ||
cadence-ttc.c | ||
dw-apb-timer.c | ||
Kconfig | ||
Makefile | ||
mchp-pit64b-timer.c | ||
mpc83xx_timer.c | ||
mtk_timer.c | ||
nomadik-mtu-timer.c | ||
omap-timer.c | ||
ostm_timer.c | ||
riscv_timer.c | ||
rockchip_timer.c | ||
sandbox_timer.c | ||
sifive_clint_timer.c | ||
sti-timer.c | ||
stm32_timer.c | ||
timer-uclass.c | ||
tsc_timer.c |