d8d33b6d4d
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL iMX6ULL SoM. CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: Variscite DART-6UL Evaluation Kit Board: Variscite DART-6UL Evaluation Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2c - MMC/SD - eMMC - USB host - UART 1 Note: LCDIF porting needs DM_VIDEO https://lists.denx.de/pipermail/u-boot/2019-April/365506.html Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
9 lines
251 B
Plaintext
9 lines
251 B
Plaintext
MX6UL_DART BOARD
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M: Parthiban Nallathambi <parthitce@gmail.com>
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S: Maintained
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F: arch/arm/dts/imx6ull-dart-6ul.dts
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F: arch/arm/dts/imx6ull-dart-6ul.dtsi
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F: board/variscite/dart_6ul/
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F: configs/variscite_dart6ul_defconfig
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F: include/configs/dart_6ul.h
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