31a4f1e5b6
Now that none of the core checks CONFIG_NET_MULTI, there's not much point in boards defining it. So scrub all references to it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
298 lines
8.7 KiB
C
298 lines
8.7 KiB
C
/*
|
|
* (C) Copyright 2005
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#ifndef __CONFIG_H
|
|
#define __CONFIG_H
|
|
|
|
/*
|
|
* High Level Configuration Options
|
|
* (easy to change)
|
|
*/
|
|
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
|
#define CONFIG_MPC5200
|
|
#define CONFIG_O2DNT 1 /* ... on O2DNT board */
|
|
|
|
#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* boot low for 16 MiB boards */
|
|
|
|
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
|
|
|
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
|
|
|
/*
|
|
* Serial console configuration
|
|
*/
|
|
#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
|
|
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
|
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
|
|
|
/*
|
|
* PCI Mapping:
|
|
* 0x40000000 - 0x4fffffff - PCI Memory
|
|
* 0x50000000 - 0x50ffffff - PCI IO Space
|
|
*/
|
|
#define CONFIG_PCI 1
|
|
#define CONFIG_PCI_PNP 1
|
|
/* #define CONFIG_PCI_SCAN_SHOW 1 */
|
|
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
|
|
|
|
#define CONFIG_PCI_MEM_BUS 0x40000000
|
|
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
|
#define CONFIG_PCI_MEM_SIZE 0x10000000
|
|
|
|
#define CONFIG_PCI_IO_BUS 0x50000000
|
|
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
|
#define CONFIG_PCI_IO_SIZE 0x01000000
|
|
|
|
#define CONFIG_SYS_XLB_PIPELINING 1
|
|
|
|
#define CONFIG_EEPRO100
|
|
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
|
#define CONFIG_NS8382X 1
|
|
|
|
/* Partitions */
|
|
#define CONFIG_MAC_PARTITION
|
|
#define CONFIG_DOS_PARTITION
|
|
#define CONFIG_ISO_PARTITION
|
|
|
|
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
|
|
|
|
|
/*
|
|
* BOOTP options
|
|
*/
|
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
#define CONFIG_BOOTP_BOOTPATH
|
|
#define CONFIG_BOOTP_GATEWAY
|
|
#define CONFIG_BOOTP_HOSTNAME
|
|
|
|
|
|
/*
|
|
* Command line configuration.
|
|
*/
|
|
#include <config_cmd_default.h>
|
|
|
|
#define CONFIG_CMD_EEPROM
|
|
#define CONFIG_CMD_FAT
|
|
#define CONFIG_CMD_I2C
|
|
#define CONFIG_CMD_NFS
|
|
#define CONFIG_CMD_MII
|
|
#define CONFIG_CMD_PING
|
|
#define CONFIG_CMD_PCI
|
|
|
|
|
|
#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
|
|
# define CONFIG_SYS_LOWBOOT 1
|
|
#else
|
|
# error "CONFIG_SYS_TEXT_BASE must be 0xFF000000"
|
|
#endif
|
|
|
|
/*
|
|
* Autobooting
|
|
*/
|
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
|
|
|
#define CONFIG_PREBOOT "echo;" \
|
|
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
|
"echo"
|
|
|
|
#undef CONFIG_BOOTARGS
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=${serverip}:${rootpath}\0" \
|
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
"addip=setenv bootargs ${bootargs} " \
|
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
":${hostname}:${netdev}:off panic=1\0" \
|
|
"flash_nfs=run nfsargs addip;" \
|
|
"bootm ${kernel_addr}\0" \
|
|
"flash_self=run ramargs addip;" \
|
|
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
|
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
|
"rootpath=/opt/eldk/ppc_82xx\0" \
|
|
"bootfile=/tftpboot/MPC5200/uImage\0" \
|
|
""
|
|
|
|
#define CONFIG_BOOTCOMMAND "run flash_self"
|
|
|
|
/*
|
|
* IPB Bus clocking configuration.
|
|
*/
|
|
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
|
|
|
|
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
|
|
/*
|
|
* PCI Bus clocking configuration
|
|
*
|
|
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
|
|
* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
|
|
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
|
|
*/
|
|
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
|
|
#endif
|
|
|
|
/*
|
|
* I2C configuration
|
|
*/
|
|
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
|
#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
|
|
|
|
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
|
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
|
|
|
/*
|
|
* EEPROM configuration:
|
|
*
|
|
* O2DNT board is equiped with Ramtron FRAM device FM24CL16
|
|
* 16 Kib Ferroelectric Nonvolatile serial RAM memory
|
|
* organized as 2048 x 8 bits and addressable as eight I2C devices
|
|
* 0x50 ... 0x57 each 256 bytes in size
|
|
*
|
|
*/
|
|
#define CONFIG_SYS_I2C_FRAM
|
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
|
/*
|
|
* There is no write delay with FRAM, write operations are performed at bus
|
|
* speed. Thus, no status polling or write delay is needed.
|
|
*/
|
|
/*#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70*/
|
|
|
|
|
|
/*
|
|
* Flash configuration
|
|
*/
|
|
#define CONFIG_SYS_FLASH_BASE 0xFF000000
|
|
#define CONFIG_SYS_FLASH_SIZE 0x01000000
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
|
|
|
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
|
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
|
|
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
|
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
|
|
#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
|
|
|
/*
|
|
* Environment settings
|
|
*/
|
|
#define CONFIG_ENV_IS_IN_FLASH 1
|
|
#define CONFIG_ENV_SIZE 0x20000
|
|
#define CONFIG_ENV_SECT_SIZE 0x20000
|
|
#define CONFIG_ENV_OVERWRITE 1
|
|
|
|
/*
|
|
* Memory map
|
|
*/
|
|
#define CONFIG_SYS_MBAR 0xF0000000
|
|
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
|
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
|
|
|
|
/* Use SRAM until RAM will be available */
|
|
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
|
|
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
|
|
|
|
|
|
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
|
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
|
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
|
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
|
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
|
|
/*
|
|
* Ethernet configuration
|
|
*/
|
|
#define CONFIG_MPC5xxx_FEC 1
|
|
#define CONFIG_MPC5xxx_FEC_MII100
|
|
/*
|
|
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
|
|
*/
|
|
/* #define CONFIG_MPC5xxx_FEC_MII10 */
|
|
#define CONFIG_PHY_ADDR 0x00
|
|
|
|
/*
|
|
* GPIO configuration
|
|
*/
|
|
/*#define CONFIG_SYS_GPS_PORT_CONFIG 0x10002004 */
|
|
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002006 /* no CAN */
|
|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
#else
|
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
|
#endif
|
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
|
|
|
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
|
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
|
|
|
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
|
|
|
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
|
|
|
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
|
#endif
|
|
|
|
/*
|
|
* Various low-level settings
|
|
*/
|
|
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
|
|
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
|
|
|
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
|
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
|
|
|
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
|
|
/*
|
|
* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
|
|
*/
|
|
#define CONFIG_SYS_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */
|
|
#else
|
|
#define CONFIG_SYS_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */
|
|
#endif
|
|
|
|
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
|
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
|
|
|
#define CONFIG_SYS_CS_BURST 0x00000000
|
|
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
|
|
|
|
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
|
|
|
|
#endif /* __CONFIG_H */
|