8a7507a8a3
CONFIG_SYS_BARGSIZE is already defined to 512 in common/image.c when not defined. Therefore, there is no point in having board configuration files define it to 512. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
145 lines
4.7 KiB
C
145 lines
4.7 KiB
C
/*
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* Configuation settings for the Renesas Solutions ECOVEC board
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*
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* Copyright (C) 2009 - 2011 Renesas Solutions Corp.
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* Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
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* Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ECOVEC_H
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#define __ECOVEC_H
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/*
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* Address Interface BusWidth
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*-----------------------------------------
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* 0x0000_0000 U-Boot 16bit
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* 0x0004_0000 Linux romImage 16bit
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* 0x0014_0000 MTD for Linux 16bit
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* 0x0400_0000 Internal I/O 16/32bit
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* 0x0800_0000 DRAM 32bit
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* 0x1800_0000 MFI 16bit
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*/
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#define CONFIG_CPU_SH7724 1
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#define CONFIG_ECOVEC 1
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#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
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#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
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#define CONFIG_DISPLAY_BOARDINFO
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SH
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
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#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
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#define CONFIG_SYS_I2C_SH_SPEED0 100000
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#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
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#define CONFIG_SYS_I2C_SH_SPEED1 100000
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#define CONFIG_SH_I2C_DATA_HIGH 4
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#define CONFIG_SH_I2C_DATA_LOW 5
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#define CONFIG_SH_I2C_CLOCK 41666666
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
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#define CONFIG_PHY_SMSC 1
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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/* USB / R8A66597 */
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#define CONFIG_USB_R8A66597_HCD
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#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
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#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
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#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
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#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
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#define CONFIG_SUPERH_ON_CHIP_R8A66597
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/* undef to save memory */
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#define CONFIG_SYS_LONGHELP
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/* Monitor Command Prompt */
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/* Buffer size for Console output */
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#define CONFIG_SYS_PBSIZE 256
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/* List of legal baudrate settings for this board */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_SCIF 1
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#define CONFIG_CONS_SCIF0 1
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/* Suppress display of console information at boot */
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE (0x88000000)
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#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
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/* Enable alternate, more extensive, memory test */
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#undef CONFIG_SYS_ALT_MEMTEST
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/* Scratch address used by the alternate memory test */
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#undef CONFIG_SYS_MEMTEST_SCRATCH
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/* Enable temporary baudrate change while serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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/* FLASH */
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_CFI
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BASE (0xA0000000)
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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/* Timeout for Flash erase operations (in ms) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
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/* Timeout for Flash write operations (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
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/* Timeout for Flash set sector lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
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/* Timeout for Flash clear lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
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/*
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* Use hardware flash sectors protection instead
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* of U-Boot software protection
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*/
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#undef CONFIG_SYS_FLASH_PROTECTION
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#undef CONFIG_SYS_DIRECT_FLASH_TFTP
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/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
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/* Monitor size */
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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/* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* ENV setting */
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 41666666
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __ECOVEC_H */
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