d640abf9c8
Add the FMan v3 nodes for the T1042D4RDB. The nodes are copied over with little modification from the Linux kernel source code. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
86 lines
1.4 KiB
Plaintext
86 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* T1042D4RDB Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019-2021 NXP
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*/
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/include/ "t104x.dtsi"
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/ {
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model = "fsl,T1042D4RDB";
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compatible = "fsl,T1042D4RDB";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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spi0 = &espi0;
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};
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};
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&soc {
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fman0: fman@400000 {
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ethernet@e0000 {
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phy-handle = <&phy_sgmii_0>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&phy_sgmii_1>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&phy_sgmii_2>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&phy_rgmii_0>;
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phy-connection-type = "rgmii";
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};
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ethernet@e8000 {
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phy-handle = <&phy_rgmii_1>;
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phy-connection-type = "rgmii";
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};
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mdio0: mdio@fc000 {
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phy_sgmii_0: ethernet-phy@2 {
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reg = <0x02>;
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};
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phy_sgmii_1: ethernet-phy@3 {
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reg = <0x03>;
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};
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phy_sgmii_2: ethernet-phy@1 {
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reg = <0x01>;
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};
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phy_rgmii_0: ethernet-phy@4 {
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reg = <0x04>;
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};
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phy_rgmii_1: ethernet-phy@5 {
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reg = <0x05>;
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};
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};
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};
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};
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&espi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <10000000>; /* input clock */
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};
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};
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/include/ "t1042si-post.dtsi"
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