15d086ded9
Device tree include file p2020-post.dtsi should be included after the board device tree file and overrides settings of the board. So it should not disable some node as board cannot enable it via normal way (it has to enable it after inclusion of p2020-post.dtsi file). Fix it by removal of explicit disable in p2020-post.dtsi file and then remove explicit post-post enable in all P2020 board device tree files. Currently no P2020 board has spi@7000 node disabled. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
60 lines
1.3 KiB
Plaintext
60 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P2020RDB-PC Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/include/ "p2020.dtsi"
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/ {
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model = "fsl,P2020RDB-PC";
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compatible = "fsl,P2020RDB-PC";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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};
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pci2: pcie@ffe08000 {
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reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
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status = "disabled";
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};
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pci1: pcie@ffe09000 {
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reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
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ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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pci0: pcie@ffe0a000 {
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reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
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ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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aliases {
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spi0 = &espi0;
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};
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};
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/include/ "p2020rdb-pc.dtsi"
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/include/ "p2020-post.dtsi"
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&espi0 {
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <10000000>; /* input clock */
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};
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};
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