206 lines
7.0 KiB
C
206 lines
7.0 KiB
C
/*
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Copyright (C) 2006 Micronas GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SCC_H
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#define _SCC_H
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#define DMA_READ 0 /* SCC read DMA */
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#define DMA_WRITE 1 /* SCC write DMA */
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#define DMA_LINEAR 0 /* DMA linear buffer access method */
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#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */
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#define DMA_START 0 /* DMA command - start DMA */
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#define DMA_STOP 1 /* DMA command - stop DMA */
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#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
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#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
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#define AGU_ACTIVE 0 /* enable AGU address calculation */
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#define AGU_BYPASS 1 /* set AGU to bypass mode */
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#define USE_NO_FH 0 /* order the DMA to not use FH */
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#define USE_FH 1 /* order the DMA to work with FH*/
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#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */
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#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */
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#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/
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#define TO_DMA_CFG 2 /* takeover command for the DMA config*/
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#define DMA_CMD_RESET 0
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#define DMA_CMD_SETUP 1
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#define DMA_CMD_START 2
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#define DMA_CMD_STOP 3
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#define DMA_STATE_RESET 0
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#define DMA_STATE_SETUP 1
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#define DMA_STATE_START 2
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#define DMA_STATE_ERROR 3
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#define SRMD 0
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#define STRM_D 1
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#define STRM_P 2
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/*
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* Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks)
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*/
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#define RESET_TIME 2 /* cycle calc see in SCC_Reset */
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struct scc_descriptor {
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char *pu_name; /* PU identifier */
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char *scc_instance; /* SCC Name */
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u32 profile; /* SCC VCI_D profile */
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u32 base_address; /* base address of the SCC unit reg shell*/
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/* SCS Interconnect configuration */
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u32 p_scc_id; /* instance number of SCC unit */
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u32 p_mci_id; /* memory channel ID */
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/* DMA Registers configuration */
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u32 p_dma_channels_rd; /* Number of Read DMA channels */
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u32 p_dma_channels_wr; /* Number of Write DMA channels */
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u32 p_dma_packet_desc; /* Number of packet descriptors */
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u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */
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int use_fh; /* the flag tells if SCC uses an FH */
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int p_si2ocp_id; /* instance number of SI2OCP unit */
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int hw_dma_cfg; /* HW or SW DMA config flag */
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int hw_dma_start; /* HW or SW DMA start/stop flag */
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u32 *buffer_tag_list; /* list of the buffer tags available */
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u32 *csize_list; /* list of the valid CSIZE values */
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};
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struct scc_dma_state {
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u32 scc_id:8; /* SCC id */
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u32 dma_id:8; /* DMA id, used for match with array idx*/
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u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */
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u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/
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u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/
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u32 dma_cmd:4; /* last executed command on this DMA */
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};
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union scc_cmd {
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u32 reg;
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struct {
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u32 res1:19; /* reserved */
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u32 drs:1; /* DMA Register Set */
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u32 rid:2; /* Register Identifier */
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u32 id:6; /* DMA Identifier */
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u32 action:4; /* DMA Command encoding */
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} bits;
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};
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union scc_dma_cfg {
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u32 reg;
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struct {
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u32 res1:17; /* reserved */
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u32 agu_mode:1; /* AGU Mode */
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u32 res2:1; /* reserved */
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u32 fh_mode:1; /* Fifo Handler */
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u32 buffer_type:1; /* Defines type of mem buffers */
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u32 mci_cfg_id:1; /* MCI_CFG register selector */
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u32 packet_cfg_id:1; /* PACKET_CFG register selector */
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u32 buffer_id:8; /* DMA Buffer Identifier */
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} bits;
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};
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union scc_debug {
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u32 reg;
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struct {
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u32 res1:20; /* reserved */
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u32 arg:8; /* SCC Debug Command Argument (#) */
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u32 cmd:4; /* SCC Debug Command Register */
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} bits;
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};
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union scc_softwareconfiguration {
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u32 reg;
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struct {
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u32 res1:28; /* reserved */
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u32 clock_status:1; /* clock on/off */
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u32 packet_select:1; /* active SCC packet id */
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u32 enable_status:1; /* enabled [1/0] */
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u32 active_status:1; /* 1=active 0=reset */
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} bits;
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};
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/*
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* System on Chip Channel ID
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*/
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enum scc_id {
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SCC_NULL = -1, /* illegal SCC identifier */
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SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */
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SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */
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SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */
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SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */
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SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */
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SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */
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SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */
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SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */
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SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */
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SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */
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SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */
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SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */
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SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */
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SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */
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SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */
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SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */
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SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */
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SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */
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SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */
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SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */
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SCC_TSIO_WR, /* SCC_TSIO Write channel */
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SCC_TSIO_RD, /* SCC_TSIO Read channel */
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SCC_TSD_WR, /* SCC_TSD Write channel */
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SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */
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SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */
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SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */
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SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */
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SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */
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SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */
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SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */
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SCC_GA_WR, /* SCC_GA Write channel */
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SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */
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SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */
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SCC_AD_RD, /* SCC_AD Read channel */
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SCC_AD_WR, /* SCC_AD Write channel */
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SCC_ABP_RD, /* SCC_ABP Read channel */
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SCC_ABP_WR, /* SCC_ABP Write channel */
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SCC_EBI_RW, /* SCC_EBI Read/Write channel */
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SCC_USB_RW, /* SCC_USB Read/Write channel */
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SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */
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SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */
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SCC_MAX /* maximum limit on the SCC id */
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};
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int scc_set_usb_address_generation_mode(u32 agu_mode);
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int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs);
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int scc_setup_dma(enum scc_id id, u32 buffer_tag,
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u32 type, u32 fh_mode, u32 drs, u32 dma_id);
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int scc_enable(enum scc_id id, u32 value);
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int scc_reset(enum scc_id id, u32 value);
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#endif /* _SCC_H */
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