79a5be820d
Adjust the code to allow beeping at different frequencies, using a calculated value for timer 2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*/
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/* i8254.h Intel 8254 PIT registers */
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#ifndef _ASMI386_I8254_H_
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#define _ASMI386_I8954_H_
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#define PIT_T0 0x00 /* PIT channel 0 count/status */
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#define PIT_T1 0x01 /* PIT channel 1 count/status */
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#define PIT_T2 0x02 /* PIT channel 2 count/status */
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#define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */
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/* PIT Command Register Bit Definitions */
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#define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */
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#define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */
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#define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */
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#define PIT_CMD_LATCH 0x00 /* Counter Latch Command */
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#define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */
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#define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */
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#define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */
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#define PIT_CMD_MODE0 0x00 /* Select mode 0 */
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#define PIT_CMD_MODE1 0x02 /* Select mode 1 */
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#define PIT_CMD_MODE2 0x04 /* Select mode 2 */
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#define PIT_CMD_MODE3 0x06 /* Select mode 3 */
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#define PIT_CMD_MODE4 0x08 /* Select mode 4 */
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#define PIT_CMD_MODE5 0x0a /* Select mode 5 */
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/* The clock frequency of the i8253/i8254 PIT */
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#define PIT_TICK_RATE 1193182
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/**
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* i8254_enable_beep() - Start a beep using the PCAT timer
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*
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* This starts beeping using the legacy i8254 timer. The beep may be silenced
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* after a delay with i8254_disable_beep().
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*
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* @frequency_hz: Frequency of beep in Hz
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* @return 0 if OK, -EINVAL if frequency_hz is 0
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*/
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int i8254_enable_beep(uint frequency_hz);
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/**
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* i8254_disable_beep() - Disable the bepper
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*
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* This stops any existing beep
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*/
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void i8254_disable_beep(void);
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#endif /* _ASMI386_I8954_H_ */
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