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u-boot/post/cpu
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Stefan Roese 28e94bb2f7 ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST 
This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test.
When cache is enabled in the SDRAM area, the values written to SDRAM
need to be flushed from cache to SDRAM using the dcfb instruction.

Without this patch the POST ECC test failed. Now its working again on
platforms with cache enabled in SDRAM.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-11-28 11:06:47 +01:00
..
mpc8xx Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
mpc83xx Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
ppc4xx ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST 2010-11-28 11:06:47 +01:00