816226d27e
Add a basic CPU driver that retrieves information about the microblaze CPU
core. cpu_ops handlers are implemented so that the "cpu" command can work
properly:
U-Boot-mONStR> cpu list
0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
U-Boot-mONStR> cpu detail
0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
ID = 0, freq = 50 MHz: L1 cache, MMU
Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from
linux.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
132 lines
2.8 KiB
C
132 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com>
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*/
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#include <common.h>
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#include <asm/cpuinfo.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(CPU_MICROBLAZE)
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/* These key value are as per MBV field in PVR0 */
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static const struct microblaze_version_map cpu_ver_lookup[] = {
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{"5.00.a", 0x01},
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{"5.00.b", 0x02},
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{"5.00.c", 0x03},
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{"6.00.a", 0x04},
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{"6.00.b", 0x06},
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{"7.00.a", 0x05},
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{"7.00.b", 0x07},
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{"7.10.a", 0x08},
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{"7.10.b", 0x09},
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{"7.10.c", 0x0a},
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{"7.10.d", 0x0b},
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{"7.20.a", 0x0c},
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{"7.20.b", 0x0d},
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{"7.20.c", 0x0e},
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{"7.20.d", 0x0f},
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{"7.30.a", 0x10},
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{"7.30.b", 0x11},
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{"8.00.a", 0x12},
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{"8.00.b", 0x13},
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{"8.10.a", 0x14},
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{"8.20.a", 0x15},
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{"8.20.b", 0x16},
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{"8.30.a", 0x17},
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{"8.40.a", 0x18},
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{"8.40.b", 0x19},
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{"8.50.a", 0x1a},
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{"8.50.b", 0x1c},
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{"8.50.c", 0x1e},
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{"9.0", 0x1b},
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{"9.1", 0x1d},
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{"9.2", 0x1f},
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{"9.3", 0x20},
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{"9.4", 0x21},
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{"9.5", 0x22},
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{"9.6", 0x23},
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{"10.0", 0x24},
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{"11.0", 0x25},
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{NULL, 0},
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};
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static const struct microblaze_version_map family_string_lookup[] = {
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{"virtex2", 0x4},
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{"virtex2pro", 0x5},
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{"spartan3", 0x6},
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{"virtex4", 0x7},
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{"virtex5", 0x8},
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{"spartan3e", 0x9},
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{"spartan3a", 0xa},
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{"spartan3an", 0xb},
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{"spartan3adsp", 0xc},
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{"spartan6", 0xd},
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{"virtex6", 0xe},
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{"virtex7", 0xf},
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/* FIXME There is no key code defined for spartan2 */
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{"spartan2", 0xf0},
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{"kintex7", 0x10},
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{"artix7", 0x11},
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{"zynq7000", 0x12},
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{"UltraScale Virtex", 0x13},
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{"UltraScale Kintex", 0x14},
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{"UltraScale+ Zynq", 0x15},
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{"UltraScale+ Virtex", 0x16},
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{"UltraScale+ Kintex", 0x17},
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{"Spartan7", 0x18},
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{NULL, 0},
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};
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static const char *lookup_string(u32 code,
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const struct microblaze_version_map *entry)
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{
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for (; entry->string; ++entry)
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if (entry->code == code)
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return entry->string;
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return "(unknown)";
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}
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static const u32 lookup_code(const char *string,
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const struct microblaze_version_map *entry)
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{
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for (; entry->string; ++entry)
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if (!strcmp(entry->string, string))
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return entry->code;
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return 0;
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}
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const char *microblaze_lookup_fpga_family_string(const u32 code)
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{
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return lookup_string(code, family_string_lookup);
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}
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const char *microblaze_lookup_cpu_version_string(const u32 code)
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{
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return lookup_string(code, cpu_ver_lookup);
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}
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const u32 microblaze_lookup_fpga_family_code(const char *string)
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{
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return lookup_code(string, family_string_lookup);
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}
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const u32 microblaze_lookup_cpu_version_code(const char *string)
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{
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return lookup_code(string, cpu_ver_lookup);
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}
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#endif /* CONFIG_CPU_MICROBLAZE */
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void microblaze_early_cpuinfo_init(void)
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{
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struct microblaze_cpuinfo *ci = gd_cpuinfo();
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ci->icache_size = CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE;
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ci->icache_line_length = 4;
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ci->dcache_size = CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE;
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ci->dcache_line_length = 4;
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}
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