5779d8d985
update for for Atmel AT91RM9200DK development kit:
- support for environment variables in DataFlash
- Atmel DataFlash AT45DB1282 support
* Patch by Jeff Carr, 11 Nov 2003:
add support for new version of 8270 processors
* Patches by George G. Davis, 05 Nov 2003:
- only pass the ARM linux initrd tag to the kernel when an initrd
is actually present
- update omap1510inn configuration file
187 lines
6.1 KiB
C
187 lines
6.1 KiB
C
/*
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* Rick Bronson <rick@efn.org>
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*
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* Configuation settings for the AT91RM9200DK board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* If we are developing, we might want to start armboot from ram
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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#define CONFIG_INIT_CRITICAL /* undef for developing */
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
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/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
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#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_BAUDRATE 115200
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/*
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* Hardware drivers
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*/
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#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
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#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
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#define CONFIG_BOOTDELAY 3
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/* #define CONFIG_ENV_OVERWRITE 1 */
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#define CONFIG_COMMANDS \
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((CONFIG_CMD_DFL | \
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CFG_CMD_DHCP ) & \
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~(CFG_CMD_BDI | \
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CFG_CMD_IMI | \
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CFG_CMD_AUTOSCRIPT | \
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CFG_CMD_FPGA | \
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CFG_CMD_MISC | \
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CFG_CMD_LOADS ))
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
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#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
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#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
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#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
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#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
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#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
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#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
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#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
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/* the following are NOP's in our implementation */
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_SETCLE(nandptr)
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
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#define CFG_MEMTEST_START PHYS_SDRAM
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#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
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#define CONFIG_DRIVER_ETHER
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_HAS_DATAFLASH 1
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#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
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#define CFG_MAX_DATAFLASH_BANKS 2
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#define CFG_MAX_DATAFLASH_PAGES 16384
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#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
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#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 40
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
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#undef CFG_ENV_IS_IN_DATAFLASH
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#ifdef CFG_ENV_IS_IN_DATAFLASH
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#define CFG_ENV_OFFSET 0x20000
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#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
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#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
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#else
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* 0x10000 */
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#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
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#endif
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#define CFG_LOAD_ADDR 0x21000000 /* default load address */
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#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
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#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
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#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
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#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CFG_PROMPT "Uboot> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#ifndef __ASSEMBLY__
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/*-----------------------------------------------------------------------
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* Board specific extension for bd_info
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*
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* This structure is embedded in the global bd_info (bd_t) structure
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* and can be used by the board specific code (eg board/...)
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*/
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struct bd_info_ext
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{
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/* helper variable for board environment handling
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*
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* env_crc_valid == 0 => uninitialised
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* env_crc_valid > 0 => environment crc in flash is valid
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* env_crc_valid < 0 => environment crc in flash is invalid
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*/
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int env_crc_valid;
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};
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#endif
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#define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to
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AT91C_TC_TIMER_DIV1_CLOCK */
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ not supported
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#endif
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#endif
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