b0cf733933
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
302 lines
9.5 KiB
C
302 lines
9.5 KiB
C
/*
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* (C) Copyright 2009-2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* icon.h - configuration for Mosaixtech ICON (440SPe)
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ICON 1 /* Board is icon */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_440SPE 1 /* Specifc SPe support */
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME icon
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */
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#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
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#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
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#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
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#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */
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#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
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#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
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#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
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#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
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#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
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#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
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#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
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/* base address of inbound PCIe window */
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#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
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#define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */
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#define CONFIG_SYS_ACE_BASE_PHYS_H 0x4
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#define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000
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#define CONFIG_SYS_FLASH_SIZE (64 << 20)
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
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#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
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#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000
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#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
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(u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
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/*
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* Initial RAM & stack pointer (placed in internal SRAM)
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*/
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* size of used area */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK
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/*
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* DDR2 SDRAM
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*/
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */
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#define CONFIG_DDR_ECC /* with ECC support */
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#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
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#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C bootstrap EEPROM */
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
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#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
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/* I2C RTC */
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#define CONFIG_RTC_M41T11
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#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
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/*
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* Video options
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*/
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_SM501
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#define CONFIG_VIDEO_SM501_32BPP
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#define CONFIG_VIDEO_SM501_PCI
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#define VIDEO_FB_LITTLE_ENDIAN
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CFG_CONSOLE_IS_IN_ENV
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#endif
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"fdt_addr=fc1e0000\0" \
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"ramdisk_addr=fc200000\0" \
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"pciconfighost=1\0" \
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"pcie_mode=RP:RP:RP\0" \
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""
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_CHIP_CONFIG
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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#define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */
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#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
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#define CONFIG_HAS_ETH0
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#define CONFIG_PHY_RESET /* reset phy upon startup */
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#define CONFIG_PHY_RESET_DELAY 1000
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#define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */
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#define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */
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/*
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* FLASH related
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*
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* PCI stuff
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*/
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/* General PCI */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/
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/* Board-specific PCI */
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#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
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#undef CONFIG_SYS_PCI_MASTER_INIT
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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/*
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* Xilinx System ACE support
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*/
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#define CONFIG_SYSTEMACE /* Enable SystemACE support */
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#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
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#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
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/*
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (Flash) initialization */
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#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(7) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | \
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EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
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EBC_BXCR_BS_64MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_16BIT)
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/* Memory Bank 1 (Xilinx System ACE controller) initialization */
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#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(4) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | \
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EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_NONDELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \
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EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_16BIT)
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/*
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* Initialize EBC CONFIG -
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* Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
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* default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
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*/
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#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
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EBC_CFG_PTD_ENABLE | \
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EBC_CFG_RTC_16PERCLK | \
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EBC_CFG_ATC_PREVIOUS | \
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EBC_CFG_DTC_PREVIOUS | \
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EBC_CFG_CTC_PREVIOUS | \
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EBC_CFG_OEO_PREVIOUS | \
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EBC_CFG_EMC_DEFAULT | \
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EBC_CFG_PME_DISABLE | \
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EBC_CFG_PR_16)
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/*
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* GPIO Setup
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*/
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#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
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#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
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#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
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#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
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#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
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GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
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GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
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GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
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#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
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#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
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#define CONFIG_SYS_GPIO_ODR 0
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#endif /* __CONFIG_H */
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