ce53fc6601
Older on-chip Blackfin bootroms do not create a dummy NMI handler, so set up one ourselves when anomaly 05000219 applies. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
158 lines
3.5 KiB
ArmAsm
158 lines
3.5 KiB
ArmAsm
/*
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* interrupt.S - trampoline default exceptions/interrupts to C handlers
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*
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* Copyright (c) 2005-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#include <config.h>
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#include <asm/blackfin.h>
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#include <asm/entry.h>
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#include <asm/ptrace.h>
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#include <asm/deferred.h>
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#include <asm/mach-common/bits/core.h>
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.text
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/* default entry point for exceptions */
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ENTRY(_trap)
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CONFIG_BFIN_SCRATCH_REG = sp;
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sp.l = LO(L1_SRAM_SCRATCH_END - 20);
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sp.h = HI(L1_SRAM_SCRATCH_END - 20);
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SAVE_ALL_SYS
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r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
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r1 = 3; /* EVT3 space */
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sp += -12;
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call _trap_c;
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sp += 12;
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#ifdef CONFIG_EXCEPTION_DEFER
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CC = R0 == 0;
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IF CC JUMP .Lexit_trap;
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/* To avoid double faults, lower our priority to IRQ5 */
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p4.l = lo(COREMMR_BASE);
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p4.h = hi(COREMMR_BASE);
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r7.h = _exception_to_level5;
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r7.l = _exception_to_level5;
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[p4 + (EVT5 - COREMMR_BASE)] = r7;
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/*
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* Save these registers, as they are only valid in exception context
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* (where we are now - as soon as we defer to IRQ5, they can change)
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*/
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p5.l = _deferred_regs;
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p5.h = _deferred_regs;
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r6 = [p4 + (DCPLB_FAULT_ADDR - COREMMR_BASE)];
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[p5 + (deferred_regs_DCPLB_FAULT_ADDR * 4)] = r6;
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r6 = [p4 + (ICPLB_FAULT_ADDR - COREMMR_BASE)];
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[p5 + (deferred_regs_ICPLB_FAULT_ADDR * 4)] = r6;
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/* Save the state of single stepping */
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r6 = SYSCFG;
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[p5 + (deferred_regs_SYSCFG * 4)] = r6;
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/* Clear it while we handle the exception in IRQ5 mode
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* RESTORE_ALL_SYS will load it, so all we need to do is store it
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* in the right place
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*/
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BITCLR(r6, SYSCFG_SSSTEP_P);
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[SP + PT_SYSCFG] = r6;
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/* Since we are going to clobber RETX, we need to save it */
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r6 = retx;
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[p5 + (deferred_regs_retx * 4)] = r6;
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/* Save the current IMASK, since we change in order to jump to level 5 */
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cli r6;
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[p5 + (deferred_regs_IMASK * 4)] = r6;
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/* Disable all interrupts, but make sure level 5 is enabled so
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* we can switch to that level.
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*/
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r6 = 0x3f;
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sti r6;
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/* Clobber RETX so we don't end up back at a faulting instruction */
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[sp + PT_RETX] = r7;
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/* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
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* clear it (re-enabling interrupts again) by the special sequence of pushing
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* RETI onto the stack. This way we can lower ourselves to IVG5 even if the
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* exception was taken after the interrupt handler was called but before it
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* got a chance to enable global interrupts itself.
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*/
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[--sp] = reti;
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sp += 4;
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RAISE 5;
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.Lexit_trap:
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#endif
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#if ANOMALY_05000257
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R7 = LC0;
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LC0 = R7;
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R7 = LC1;
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LC1 = R7;
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#endif
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RESTORE_ALL_SYS
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sp = CONFIG_BFIN_SCRATCH_REG;
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rtx;
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ENDPROC(_trap)
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#ifdef CONFIG_EXCEPTION_DEFER
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/* Deferred (IRQ5) exceptions */
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ENTRY(_exception_to_level5)
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SAVE_ALL_SYS
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/* Now we have to fix things up */
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p4.l = lo(EVT5);
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p4.h = hi(EVT5);
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r0.l = _evt_default;
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r0.h = _evt_default;
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[p4] = r0;
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csync;
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p4.l = _deferred_regs;
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p4.h = _deferred_regs;
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r0 = [p4 + (deferred_regs_retx * 4)];
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[sp + PT_PC] = r0;
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r0 = [p4 + (deferred_regs_SYSCFG * 4)];
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[sp + PT_SYSCFG] = r0;
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r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
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r1 = 5; /* EVT5 space */
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sp += -12;
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call _trap_c;
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sp += 12;
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/* Restore IMASK */
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r0 = [p4 + (deferred_regs_IMASK * 4)];
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sti r0;
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RESTORE_ALL_SYS
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rti;
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ENDPROC(_exception_to_level5)
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#endif
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/* default entry point for interrupts */
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ENTRY(_evt_default)
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SAVE_ALL_SYS
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r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
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sp += -12;
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call _bfin_panic;
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sp += 12;
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RESTORE_ALL_SYS
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rti;
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ENDPROC(_evt_default)
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/* NMI handler */
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ENTRY(_evt_nmi)
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rtn;
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ENDPROC(_evt_nmi)
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