a913c03c16
The SPL payload offset when booting from SPI defaults to CONFIG_SYS_SPI_U_BOOT_OFFS but can be overridden by u-boot,spl-payload-offset. The Device Tree for Puma Haikou has this property so there's no need to have this one option in the defconfig, especially since they are not in sync and therefore confusing. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
118 lines
3.0 KiB
Plaintext
118 lines
3.0 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SPL_GPIO=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
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CONFIG_SPL_TEXT_BASE=0xff8c2000
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
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CONFIG_TARGET_PUMA_RK3399=y
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CONFIG_DEBUG_UART_BASE=0xFF180000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_SYS_LOAD_ADDR=0x800800
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CONFIG_DEBUG_UART=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SPL_MAX_SIZE=0x2e000
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CONFIG_SPL_PAD_TO=0x7f8000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0xff8e0000
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CONFIG_SPL_BSS_MAX_SIZE=0x10000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK=0xff8effff
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
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CONFIG_SPL_I2C=y
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CONFIG_SPL_POWER=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_BMP=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_NOWHERE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_ENV_SPI_MAX_HZ=50000000
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SYS_MMC_ENV_DEV=1
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CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_GPIO_HOG=y
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CONFIG_SPL_GPIO_HOG=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_ROCKCHIP_EFUSE=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_SF_DEFAULT_SPEED=20000000
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_TYPEC=y
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CONFIG_DM_PMIC_FAN53555=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_SPL_PMIC_RK8XX=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_DM_RESET=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_ISL1208=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_ROCKCHIP_SPI=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_DM_VIDEO=y
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# CONFIG_VIDEO_BPP8 is not set
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CONFIG_DISPLAY=y
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CONFIG_VIDEO_ROCKCHIP=y
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CONFIG_DISPLAY_ROCKCHIP_HDMI=y
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CONFIG_BMP_16BPP=y
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CONFIG_BMP_24BPP=y
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CONFIG_BMP_32BPP=y
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CONFIG_ERRNO_STR=y
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