40c642bc19
This patch adds the NAND SPL framework needed to boot i.MX31 boards from NAND. It has been tested on a i.MX31 PDK board with large page NAND. Small page NANDs should work as well, but this has not been tested. Note: The i.MX31 NFC uses a non-standard layout for large page NANDs, whether this is compatible with a particular setup depends on how the NAND device is programmed by the flash programmer (e.g. JTAG debugger). The patch is based on the work by Maxim Artamonov. Signed-off-by: Maxim Artamonov <scn1874@yandex.ru> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
110 lines
2.6 KiB
C
110 lines
2.6 KiB
C
/*
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*
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* (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FSL_NFC_H
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#define __FSL_NFC_H
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/*
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* Register map and bit definitions for the Freescale NAND Flash
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* Controller present in i.MX31 and other devices.
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*/
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struct fsl_nfc_regs {
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u32 main_area0[128]; /* @0x000 */
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u32 main_area1[128];
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u32 main_area2[128];
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u32 main_area3[128];
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u32 spare_area0[4];
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u32 spare_area1[4];
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u32 spare_area2[4];
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u32 spare_area3[4];
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u32 reserved1[64 - 16 + 64 * 5];
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u16 bufsiz; /* @ 0xe00 */
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u16 reserved2;
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u16 buffer_address;
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u16 flash_add;
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u16 flash_cmd;
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u16 configuration;
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u16 ecc_status_result;
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u16 ecc_rslt_main_area;
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u16 ecc_rslt_spare_area;
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u16 nf_wr_prot;
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u16 unlock_start_blk_add;
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u16 unlock_end_blk_add;
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u16 nand_flash_wr_pr_st;
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u16 nand_flash_config1;
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u16 nand_flash_config2;
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};
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/*
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* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
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* operation
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*/
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#define NFC_CMD 0x1
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/*
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* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
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* operation
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*/
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#define NFC_ADDR 0x2
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/*
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* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
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* operation
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*/
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#define NFC_INPUT 0x4
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/*
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* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
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* Output operation
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*/
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#define NFC_OUTPUT 0x8
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/*
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* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
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* operation
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*/
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#define NFC_ID 0x10
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/*
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* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
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* Status operation
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*/
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#define NFC_STATUS 0x20
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/*
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* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
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* operation
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*/
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#define NFC_INT 0x8000
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#define NFC_SP_EN (1 << 2)
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#define NFC_ECC_EN (1 << 3)
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#define NFC_INT_MSK (1 << 4)
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#define NFC_BIG (1 << 5)
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#define NFC_RST (1 << 6)
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#define NFC_CE (1 << 7)
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#define NFC_ONE_CYCLE (1 << 8)
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#endif /* __FSL_NFC_H */
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