163 lines
4.1 KiB
C
163 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <p2sb.h>
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#include <pch.h>
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#include <pci.h>
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#include <syscon.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/intel_pinctrl_defs.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/gpio.h>
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#include <dt-bindings/gpio/x86-gpio.h>
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static int intel_gpio_direction_input(struct udevice *dev, uint offset)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
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pcr_clrsetbits32(pinctrl, config_offset,
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PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
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PAD_CFG0_RX_DISABLE,
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PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE);
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return 0;
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}
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static int intel_gpio_direction_output(struct udevice *dev, uint offset,
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int value)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
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pcr_clrsetbits32(pinctrl, config_offset,
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PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
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PAD_CFG0_TX_DISABLE | PAD_CFG0_TX_STATE,
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PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE |
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(value ? PAD_CFG0_TX_STATE : 0));
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return 0;
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}
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static int intel_gpio_get_value(struct udevice *dev, uint offset)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint mode, rx_tx;
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u32 reg;
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reg = intel_pinctrl_get_config_reg(pinctrl, offset);
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mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
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if (!mode) {
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rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
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if (rx_tx == PAD_CFG0_TX_DISABLE)
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return reg & PAD_CFG0_RX_STATE ? 1 : 0;
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else if (rx_tx == PAD_CFG0_RX_DISABLE)
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return reg & PAD_CFG0_TX_STATE ? 1 : 0;
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}
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return 0;
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}
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static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
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pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
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value ? PAD_CFG0_TX_STATE : 0);
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return 0;
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}
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static int intel_gpio_get_function(struct udevice *dev, uint offset)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint mode, rx_tx;
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u32 reg;
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reg = intel_pinctrl_get_config_reg(pinctrl, offset);
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mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
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if (!mode) {
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rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
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if (rx_tx == PAD_CFG0_TX_DISABLE)
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return GPIOF_INPUT;
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else if (rx_tx == PAD_CFG0_RX_DISABLE)
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return GPIOF_OUTPUT;
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}
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return GPIOF_FUNC;
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}
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static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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struct udevice *pinctrl, *dev;
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int gpio, ret;
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/*
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* GPIO numbers are global in the device tree so it doesn't matter
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* which one is used
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*/
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gpio = args->args[0];
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ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
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if (ret)
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return log_msg_ret("bad", ret);
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device_find_first_child(pinctrl, &dev);
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if (!dev)
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return log_msg_ret("no child", -ENOENT);
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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desc->dev = dev;
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return 0;
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}
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static int intel_gpio_probe(struct udevice *dev)
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{
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return 0;
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}
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static int intel_gpio_ofdata_to_platdata(struct udevice *dev)
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{
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struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
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struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
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const struct pad_community *comm = pinctrl_priv->comm;
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upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
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upriv->bank_name = dev->name;
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return 0;
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}
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static const struct dm_gpio_ops gpio_intel_ops = {
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.direction_input = intel_gpio_direction_input,
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.direction_output = intel_gpio_direction_output,
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.get_value = intel_gpio_get_value,
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.set_value = intel_gpio_set_value,
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.get_function = intel_gpio_get_function,
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.xlate = intel_gpio_xlate,
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};
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static const struct udevice_id intel_intel_gpio_ids[] = {
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{ .compatible = "intel,gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_intel) = {
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.name = "gpio_intel",
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.id = UCLASS_GPIO,
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.of_match = intel_intel_gpio_ids,
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.ops = &gpio_intel_ops,
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.ofdata_to_platdata = intel_gpio_ofdata_to_platdata,
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.probe = intel_gpio_probe,
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};
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