38b6686f05
Add pinctrl driver for i.MX8. The pads configuration is controlled by SCU, so need to ask SCU to configure pads through scfw API. Add pinctrl-scu to invoke sc_pad_set to configure pads. Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms which could directly configure pads from Acore side. Add CONFIG_PINCTRL_IMX8 as the built gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <errno.h>
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#include <linux/bitops.h>
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#include <asm/io.h>
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#include <asm/arch/sci/sci.h>
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#include <misc.h>
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#include "pinctrl-imx.h"
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#define PADRING_IFMUX_EN_SHIFT 31
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#define PADRING_IFMUX_EN_MASK BIT(31)
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#define PADRING_GP_EN_SHIFT 30
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#define PADRING_GP_EN_MASK BIT(30)
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#define PADRING_IFMUX_SHIFT 27
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#define PADRING_IFMUX_MASK GENMASK(29, 27)
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static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad,
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u32 mux, u32 val)
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{
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int ret;
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/*
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* Mux should be done in pmx set, but we do not have a good api
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* to handle that in scfw, so config it in pad conf func
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*/
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val |= PADRING_IFMUX_EN_MASK;
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val |= PADRING_GP_EN_MASK;
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val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK;
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ret = sc_pad_set(-1, pad, val);
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if (ret)
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printf("%s %d\n", __func__, ret);
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return 0;
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}
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int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data,
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int npins)
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{
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int pin_id, mux, config_val;
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int i, j = 0;
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int ret;
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/*
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* Refer to linux documentation for details:
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* Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
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*/
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for (i = 0; i < npins; i++) {
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pin_id = pin_data[j++];
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mux = pin_data[j++];
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config_val = pin_data[j++];
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ret = imx_pinconf_scu_set(info, pin_id, mux, config_val);
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if (ret)
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printf("Set pin %d, mux %d, val %d, error\n", pin_id,
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mux, config_val);
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}
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return 0;
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}
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