9a07e8094c
ns8382x driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
865 lines
23 KiB
C
865 lines
23 KiB
C
/*
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ns8382x.c: A U-Boot driver for the NatSemi DP8382[01].
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ported by: Mark A. Rakes (mark_rakes@vivato.net)
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Adapted from:
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1. an Etherboot driver for DP8381[56] written by:
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Copyright (C) 2001 Entity Cyber, Inc.
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This development of this Etherboot driver was funded by
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Sicom Systems: http://www.sicompos.com/
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Author: Marty Connor (mdc@thinguin.org)
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Adapted from a Linux driver which was written by Donald Becker
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This software may be used and distributed according to the terms
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of the GNU Public License (GPL), incorporated herein by reference.
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2. A Linux driver by Donald Becker, ns820.c:
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Written/copyright 1999-2002 by Donald Becker.
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This software may be used and distributed according to the terms of
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the GNU General Public License (GPL), incorporated herein by reference.
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Drivers based on or derived from this code fall under the GPL and must
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retain the authorship, copyright and license notice. This file is not
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a complete program and may only be used when the entire operating
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system is licensed under the GPL. License for under other terms may be
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available. Contact the original author for details.
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The original author may be reached as becker@scyld.com, or at
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Scyld Computing Corporation
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410 Severn Ave., Suite 210
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Annapolis MD 21403
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Support information and updates available at
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http://www.scyld.com/network/netsemi.html
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Datasheets available from:
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http://www.national.com/pf/DP/DP83820.html
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http://www.national.com/pf/DP/DP83821.html
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*/
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/* Revision History
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* October 2002 mar 1.0
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* Initial U-Boot Release.
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* Tested with Netgear GA622T (83820)
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* and SMC9452TX (83821)
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* NOTE: custom boards with these chips may (likely) require
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* a programmed EEPROM device (if present) in order to work
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* correctly.
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*/
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/* Includes */
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <pci.h>
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/* defines */
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#define DSIZE 0x00000FFF
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#define ETH_ALEN 6
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#define CRC_SIZE 4
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#define TOUT_LOOP 500000
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#define TX_BUF_SIZE 1536
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#define RX_BUF_SIZE 1536
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#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
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enum register_offsets {
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ChipCmd = 0x00,
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ChipConfig = 0x04,
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EECtrl = 0x08,
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IntrMask = 0x14,
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IntrEnable = 0x18,
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TxRingPtr = 0x20,
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TxRingPtrHi = 0x24,
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TxConfig = 0x28,
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RxRingPtr = 0x30,
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RxRingPtrHi = 0x34,
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RxConfig = 0x38,
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PriQueue = 0x3C,
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RxFilterAddr = 0x48,
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RxFilterData = 0x4C,
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ClkRun = 0xCC,
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PCIPM = 0x44,
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};
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enum ChipCmdBits {
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ChipReset = 0x100,
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RxReset = 0x20,
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TxReset = 0x10,
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RxOff = 0x08,
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RxOn = 0x04,
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TxOff = 0x02,
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TxOn = 0x01
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};
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enum ChipConfigBits {
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LinkSts = 0x80000000,
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GigSpeed = 0x40000000,
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HundSpeed = 0x20000000,
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FullDuplex = 0x10000000,
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TBIEn = 0x01000000,
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Mode1000 = 0x00400000,
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T64En = 0x00004000,
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D64En = 0x00001000,
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M64En = 0x00000800,
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PhyRst = 0x00000400,
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PhyDis = 0x00000200,
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ExtStEn = 0x00000100,
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BEMode = 0x00000001,
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};
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#define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
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enum TxConfig_bits {
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TxDrthMask = 0x000000ff,
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TxFlthMask = 0x0000ff00,
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TxMxdmaMask = 0x00700000,
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TxMxdma_8 = 0x00100000,
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TxMxdma_16 = 0x00200000,
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TxMxdma_32 = 0x00300000,
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TxMxdma_64 = 0x00400000,
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TxMxdma_128 = 0x00500000,
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TxMxdma_256 = 0x00600000,
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TxMxdma_512 = 0x00700000,
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TxMxdma_1024 = 0x00000000,
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TxCollRetry = 0x00800000,
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TxAutoPad = 0x10000000,
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TxMacLoop = 0x20000000,
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TxHeartIgn = 0x40000000,
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TxCarrierIgn = 0x80000000
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};
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enum RxConfig_bits {
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RxDrthMask = 0x0000003e,
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RxMxdmaMask = 0x00700000,
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RxMxdma_8 = 0x00100000,
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RxMxdma_16 = 0x00200000,
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RxMxdma_32 = 0x00300000,
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RxMxdma_64 = 0x00400000,
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RxMxdma_128 = 0x00500000,
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RxMxdma_256 = 0x00600000,
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RxMxdma_512 = 0x00700000,
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RxMxdma_1024 = 0x00000000,
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RxAcceptLenErr = 0x04000000,
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RxAcceptLong = 0x08000000,
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RxAcceptTx = 0x10000000,
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RxStripCRC = 0x20000000,
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RxAcceptRunt = 0x40000000,
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RxAcceptErr = 0x80000000,
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};
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/* Bits in the RxMode register. */
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enum rx_mode_bits {
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RxFilterEnable = 0x80000000,
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AcceptAllBroadcast = 0x40000000,
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AcceptAllMulticast = 0x20000000,
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AcceptAllUnicast = 0x10000000,
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AcceptPerfectMatch = 0x08000000,
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};
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typedef struct _BufferDesc {
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u32 link;
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u32 bufptr;
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vu_long cmdsts;
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u32 extsts; /*not used here */
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} BufferDesc;
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/* Bits in network_desc.status */
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enum desc_status_bits {
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DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
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DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
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DescSizeMask = 0xfff,
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DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
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DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
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DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
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DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
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DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
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DescRxDest = 0x01800000, DescRxLong = 0x00400000,
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DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
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DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
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DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
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};
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/* Bits in MEAR */
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enum mii_reg_bits {
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MDIO_ShiftClk = 0x0040,
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MDIO_EnbOutput = 0x0020,
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MDIO_Data = 0x0010,
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};
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/* PHY Register offsets. */
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enum phy_reg_offsets {
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BMCR = 0x00,
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BMSR = 0x01,
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PHYIDR1 = 0x02,
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PHYIDR2 = 0x03,
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ANAR = 0x04,
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KTCR = 0x09,
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};
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/* basic mode control register bits */
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enum bmcr_bits {
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Bmcr_Reset = 0x8000,
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Bmcr_Loop = 0x4000,
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Bmcr_Speed0 = 0x2000,
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Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */
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Bmcr_RstAutoNeg = 0x0200,
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Bmcr_Duplex = 0x0100,
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Bmcr_Speed1 = 0x0040,
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Bmcr_Force10H = 0x0000,
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Bmcr_Force10F = 0x0100,
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Bmcr_Force100H = 0x2000,
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Bmcr_Force100F = 0x2100,
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Bmcr_Force1000H = 0x0040,
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Bmcr_Force1000F = 0x0140,
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};
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/* auto negotiation advertisement register */
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enum anar_bits {
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anar_adv_100F = 0x0100,
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anar_adv_100H = 0x0080,
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anar_adv_10F = 0x0040,
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anar_adv_10H = 0x0020,
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anar_ieee_8023 = 0x0001,
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};
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/* 1K-base T control register */
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enum ktcr_bits {
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ktcr_adv_1000H = 0x0100,
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ktcr_adv_1000F = 0x0200,
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};
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/* Globals */
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static u32 SavedClkRun;
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static unsigned int cur_rx;
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static unsigned int rx_config;
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static unsigned int tx_config;
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/* Note: transmit and receive buffers and descriptors must be
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long long word aligned */
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static BufferDesc txd __attribute__ ((aligned(8)));
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static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8)));
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static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8)));
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static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
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__attribute__ ((aligned(8)));
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/* Function Prototypes */
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static int mdio_read(struct eth_device *dev, int phy_id, int addr);
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static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value);
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static void mdio_sync(struct eth_device *dev, u32 offset);
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static int ns8382x_init(struct eth_device *dev, bd_t * bis);
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static void ns8382x_reset(struct eth_device *dev);
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static void ns8382x_init_rxfilter(struct eth_device *dev);
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static void ns8382x_init_txd(struct eth_device *dev);
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static void ns8382x_init_rxd(struct eth_device *dev);
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static void ns8382x_set_rx_mode(struct eth_device *dev);
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static void ns8382x_check_duplex(struct eth_device *dev);
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static int ns8382x_send(struct eth_device *dev, volatile void *packet,
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int length);
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static int ns8382x_poll(struct eth_device *dev);
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static void ns8382x_disable(struct eth_device *dev);
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static struct pci_device_id supported[] = {
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{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820},
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{}
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};
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#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
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#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
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static inline int
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INW(struct eth_device *dev, u_long addr)
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{
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return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
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}
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static int
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INL(struct eth_device *dev, u_long addr)
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{
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return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
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}
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static inline void
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OUTW(struct eth_device *dev, int command, u_long addr)
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{
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*(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
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}
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static inline void
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OUTL(struct eth_device *dev, int command, u_long addr)
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{
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*(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
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}
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/* Function: ns8382x_initialize
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* Description: Retrieves the MAC address of the card, and sets up some
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* globals required by other routines, and initializes the NIC, making it
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* ready to send and receive packets.
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* Side effects: initializes ns8382xs, ready to recieve packets.
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* Returns: int: number of cards found
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*/
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int
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ns8382x_initialize(bd_t * bis)
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{
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pci_dev_t devno;
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int card_number = 0;
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struct eth_device *dev;
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u32 iobase, status;
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int i, idx = 0;
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u32 phyAddress;
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u32 tmp;
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u32 chip_config;
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while (1) { /* Find PCI device(s) */
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if ((devno = pci_find_devices(supported, idx++)) < 0)
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break;
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pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
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iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
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#ifdef NS8382X_DEBUG
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printf("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);
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#endif
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pci_write_config_dword(devno, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Check if I/O accesses and Bus Mastering are enabled. */
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pci_read_config_dword(devno, PCI_COMMAND, &status);
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if (!(status & PCI_COMMAND_MEMORY)) {
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printf("Error: Can not enable MEM access.\n");
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continue;
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} else if (!(status & PCI_COMMAND_MASTER)) {
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printf("Error: Can not enable Bus Mastering.\n");
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continue;
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}
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dev = (struct eth_device *) malloc(sizeof *dev);
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if (!dev) {
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printf("ns8382x: Can not allocate memory\n");
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break;
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}
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memset(dev, 0, sizeof(*dev));
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sprintf(dev->name, "dp8382x#%d", card_number);
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dev->iobase = bus_to_phys(iobase);
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dev->priv = (void *) devno;
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dev->init = ns8382x_init;
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dev->halt = ns8382x_disable;
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dev->send = ns8382x_send;
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dev->recv = ns8382x_poll;
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/* ns8382x has a non-standard PM control register
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* in PCI config space. Some boards apparently need
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* to be brought to D0 in this manner. */
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pci_read_config_dword(devno, PCIPM, &tmp);
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if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */
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u32 newtmp = tmp & ~(0x03 | 0x100);
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pci_write_config_dword(devno, PCIPM, newtmp);
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}
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/* get MAC address */
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for (i = 0; i < 3; i++) {
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u32 data;
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char *mac = (char *)&dev->enetaddr[i * 2];
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OUTL(dev, i * 2, RxFilterAddr);
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data = INL(dev, RxFilterData);
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*mac++ = data;
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*mac++ = data >> 8;
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}
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/* get PHY address, can't be zero */
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for (phyAddress = 1; phyAddress < 32; phyAddress++) {
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u32 rev, phy1;
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phy1 = mdio_read(dev, phyAddress, PHYIDR1);
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if (phy1 == 0x2000) { /*check for 83861/91 */
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rev = mdio_read(dev, phyAddress, PHYIDR2);
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if ((rev & ~(0x000f)) == 0x00005c50 ||
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(rev & ~(0x000f)) == 0x00005c60) {
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#ifdef NS8382X_DEBUG
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printf("phy rev is %x\n", rev);
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printf("phy address is %x\n",
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phyAddress);
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#endif
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break;
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}
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}
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}
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/* set phy to autonegotiate && advertise everything */
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mdio_write(dev, phyAddress, KTCR,
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(ktcr_adv_1000H | ktcr_adv_1000F));
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mdio_write(dev, phyAddress, ANAR,
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(anar_adv_100F | anar_adv_100H | anar_adv_10H |
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anar_adv_10F | anar_ieee_8023));
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mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */
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mdio_write(dev, phyAddress, BMCR,
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(Bmcr_AutoNegEn | Bmcr_RstAutoNeg));
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/* Reset the chip to erase any previous misconfiguration. */
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OUTL(dev, (ChipReset), ChipCmd);
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chip_config = INL(dev, ChipConfig);
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/* reset the phy */
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OUTL(dev, (chip_config | PhyRst), ChipConfig);
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/* power up and initialize transceiver */
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OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig);
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mdio_sync(dev, EECtrl);
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#ifdef NS8382X_DEBUG
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{
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u32 chpcfg =
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INL(dev, ChipConfig) ^ SpeedStatus_Polarity;
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printf("%s: Transceiver 10%s %s duplex.\n", dev->name,
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(chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed)
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? "0" : "",
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chpcfg & FullDuplex ? "full" : "half");
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printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
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dev->enetaddr[0], dev->enetaddr[1],
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dev->enetaddr[2], dev->enetaddr[3],
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dev->enetaddr[4], dev->enetaddr[5]);
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}
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#endif
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/* Disable PME:
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* The PME bit is initialized from the EEPROM contents.
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* PCI cards probably have PME disabled, but motherboard
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* implementations may have PME set to enable WakeOnLan.
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* With PME set the chip will scan incoming packets but
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* nothing will be written to memory. */
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SavedClkRun = INL(dev, ClkRun);
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OUTL(dev, SavedClkRun & ~0x100, ClkRun);
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eth_register(dev);
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card_number++;
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pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);
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udelay(10 * 1000);
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}
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return card_number;
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}
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/* MII transceiver control section.
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Read and write MII registers using software-generated serial MDIO
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protocol. See the MII specifications or DP83840A data sheet for details.
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The maximum data clock rate is 2.5 MHz. To meet minimum timing we
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must flush writes to the PCI bus with a PCI read. */
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#define mdio_delay(mdio_addr) INL(dev, mdio_addr)
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#define MDIO_EnbIn (0)
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#define MDIO_WRITE0 (MDIO_EnbOutput)
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#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
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/* Generate the preamble required for initial synchronization and
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a few older transceivers. */
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static void
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mdio_sync(struct eth_device *dev, u32 offset)
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{
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int bits = 32;
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/* Establish sync by sending at least 32 logic ones. */
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while (--bits >= 0) {
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OUTL(dev, MDIO_WRITE1, offset);
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mdio_delay(offset);
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OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset);
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mdio_delay(offset);
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}
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}
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static int
|
|
mdio_read(struct eth_device *dev, int phy_id, int addr)
|
|
{
|
|
int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;
|
|
int i, retval = 0;
|
|
|
|
/* Shift the read command bits out. */
|
|
for (i = 15; i >= 0; i--) {
|
|
int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
|
|
|
|
OUTL(dev, dataval, EECtrl);
|
|
mdio_delay(EECtrl);
|
|
OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
|
|
mdio_delay(EECtrl);
|
|
}
|
|
/* Read the two transition, 16 data, and wire-idle bits. */
|
|
for (i = 19; i > 0; i--) {
|
|
OUTL(dev, MDIO_EnbIn, EECtrl);
|
|
mdio_delay(EECtrl);
|
|
retval =
|
|
(retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);
|
|
OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
|
|
mdio_delay(EECtrl);
|
|
}
|
|
return (retval >> 1) & 0xffff;
|
|
}
|
|
|
|
static void
|
|
mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
|
|
{
|
|
int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;
|
|
int i;
|
|
|
|
/* Shift the command bits out. */
|
|
for (i = 31; i >= 0; i--) {
|
|
int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
|
|
|
|
OUTL(dev, dataval, EECtrl);
|
|
mdio_delay(EECtrl);
|
|
OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
|
|
mdio_delay(EECtrl);
|
|
}
|
|
/* Clear out extra bits. */
|
|
for (i = 2; i > 0; i--) {
|
|
OUTL(dev, MDIO_EnbIn, EECtrl);
|
|
mdio_delay(EECtrl);
|
|
OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
|
|
mdio_delay(EECtrl);
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Function: ns8382x_init
|
|
* Description: resets the ethernet controller chip and configures
|
|
* registers and data structures required for sending and receiving packets.
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
* returns: int.
|
|
*/
|
|
|
|
static int
|
|
ns8382x_init(struct eth_device *dev, bd_t * bis)
|
|
{
|
|
u32 config;
|
|
|
|
ns8382x_reset(dev);
|
|
|
|
/* Disable PME:
|
|
* The PME bit is initialized from the EEPROM contents.
|
|
* PCI cards probably have PME disabled, but motherboard
|
|
* implementations may have PME set to enable WakeOnLan.
|
|
* With PME set the chip will scan incoming packets but
|
|
* nothing will be written to memory. */
|
|
OUTL(dev, SavedClkRun & ~0x100, ClkRun);
|
|
|
|
ns8382x_init_rxfilter(dev);
|
|
ns8382x_init_txd(dev);
|
|
ns8382x_init_rxd(dev);
|
|
|
|
/*set up ChipConfig */
|
|
config = INL(dev, ChipConfig);
|
|
/*turn off 64 bit ops && Ten-bit interface
|
|
* && big-endian mode && extended status */
|
|
config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn);
|
|
OUTL(dev, config, ChipConfig);
|
|
|
|
/* Configure the PCI bus bursts and FIFO thresholds. */
|
|
tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
|
|
| TxCollRetry | TxMxdma_1024 | (0x1002);
|
|
rx_config = RxMxdma_1024 | 0x20;
|
|
#ifdef NS8382X_DEBUG
|
|
printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
|
|
printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
|
|
#endif
|
|
OUTL(dev, tx_config, TxConfig);
|
|
OUTL(dev, rx_config, RxConfig);
|
|
|
|
/*turn off priority queueing */
|
|
OUTL(dev, 0x0, PriQueue);
|
|
|
|
ns8382x_check_duplex(dev);
|
|
ns8382x_set_rx_mode(dev);
|
|
|
|
OUTL(dev, (RxOn | TxOn), ChipCmd);
|
|
return 1;
|
|
}
|
|
|
|
/* Function: ns8382x_reset
|
|
* Description: soft resets the controller chip
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
* Returns: void.
|
|
*/
|
|
static void
|
|
ns8382x_reset(struct eth_device *dev)
|
|
{
|
|
OUTL(dev, ChipReset, ChipCmd);
|
|
while (INL(dev, ChipCmd))
|
|
/*wait until done */ ;
|
|
OUTL(dev, 0, IntrMask);
|
|
OUTL(dev, 0, IntrEnable);
|
|
}
|
|
|
|
/* Function: ns8382x_init_rxfilter
|
|
* Description: sets receive filter address to our MAC address
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
* returns: void.
|
|
*/
|
|
|
|
static void
|
|
ns8382x_init_rxfilter(struct eth_device *dev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ETH_ALEN; i += 2) {
|
|
OUTL(dev, i, RxFilterAddr);
|
|
OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
|
|
RxFilterData);
|
|
}
|
|
}
|
|
|
|
/* Function: ns8382x_init_txd
|
|
* Description: initializes the Tx descriptor
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
* returns: void.
|
|
*/
|
|
|
|
static void
|
|
ns8382x_init_txd(struct eth_device *dev)
|
|
{
|
|
txd.link = (u32) 0;
|
|
txd.bufptr = cpu_to_le32((u32) & txb[0]);
|
|
txd.cmdsts = (u32) 0;
|
|
txd.extsts = (u32) 0;
|
|
|
|
OUTL(dev, 0x0, TxRingPtrHi);
|
|
OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
|
|
#ifdef NS8382X_DEBUG
|
|
printf("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n",
|
|
INL(dev, TxRingPtr), &txd);
|
|
#endif
|
|
}
|
|
|
|
/* Function: ns8382x_init_rxd
|
|
* Description: initializes the Rx descriptor ring
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
* Returns: void.
|
|
*/
|
|
|
|
static void
|
|
ns8382x_init_rxd(struct eth_device *dev)
|
|
{
|
|
int i;
|
|
|
|
OUTL(dev, 0x0, RxRingPtrHi);
|
|
|
|
cur_rx = 0;
|
|
for (i = 0; i < NUM_RX_DESC; i++) {
|
|
rxd[i].link =
|
|
cpu_to_le32((i + 1 <
|
|
NUM_RX_DESC) ? (u32) & rxd[i +
|
|
1] : (u32) &
|
|
rxd[0]);
|
|
rxd[i].extsts = cpu_to_le32((u32) 0x0);
|
|
rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
|
|
rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
|
|
#ifdef NS8382X_DEBUG
|
|
printf
|
|
("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
|
|
i, &rxd[i], le32_to_cpu(rxd[i].link),
|
|
le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
|
|
#endif
|
|
}
|
|
OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr);
|
|
|
|
#ifdef NS8382X_DEBUG
|
|
printf("ns8382x_init_rxd: RX descriptor register loaded with: %X\n",
|
|
INL(dev, RxRingPtr));
|
|
#endif
|
|
}
|
|
|
|
/* Function: ns8382x_set_rx_mode
|
|
* Description:
|
|
* sets the receive mode to accept all broadcast packets and packets
|
|
* with our MAC address, and reject all multicast packets.
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
* Returns: void.
|
|
*/
|
|
|
|
static void
|
|
ns8382x_set_rx_mode(struct eth_device *dev)
|
|
{
|
|
u32 rx_mode = 0x0;
|
|
/*spec says RxFilterEnable has to be 0 for rest of
|
|
* this stuff to be properly configured. Linux driver
|
|
* seems to support this*/
|
|
/* OUTL(dev, rx_mode, RxFilterAddr);*/
|
|
rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch);
|
|
OUTL(dev, rx_mode, RxFilterAddr);
|
|
printf("ns8382x_set_rx_mode: set to %X\n", rx_mode);
|
|
/*now we turn RxFilterEnable back on */
|
|
/*rx_mode |= RxFilterEnable;
|
|
OUTL(dev, rx_mode, RxFilterAddr);*/
|
|
}
|
|
|
|
static void
|
|
ns8382x_check_duplex(struct eth_device *dev)
|
|
{
|
|
int gig = 0;
|
|
int hun = 0;
|
|
int duplex = 0;
|
|
int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity);
|
|
|
|
duplex = (config & FullDuplex) ? 1 : 0;
|
|
gig = (config & GigSpeed) ? 1 : 0;
|
|
hun = (config & HundSpeed) ? 1 : 0;
|
|
#ifdef NS8382X_DEBUG
|
|
printf("%s: Setting 10%s %s-duplex based on negotiated link"
|
|
" capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
|
|
duplex ? "full" : "half");
|
|
#endif
|
|
if (duplex) {
|
|
rx_config |= RxAcceptTx;
|
|
tx_config |= (TxCarrierIgn | TxHeartIgn);
|
|
} else {
|
|
rx_config &= ~RxAcceptTx;
|
|
tx_config &= ~(TxCarrierIgn | TxHeartIgn);
|
|
}
|
|
#ifdef NS8382X_DEBUG
|
|
printf("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
|
|
printf("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
|
|
#endif
|
|
OUTL(dev, tx_config, TxConfig);
|
|
OUTL(dev, rx_config, RxConfig);
|
|
|
|
/*if speed is 10 or 100, remove MODE1000,
|
|
* if it's 1000, then set it */
|
|
config = INL(dev, ChipConfig);
|
|
if (gig)
|
|
config |= Mode1000;
|
|
else
|
|
config &= ~Mode1000;
|
|
|
|
#ifdef NS8382X_DEBUG
|
|
printf("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns");
|
|
#endif
|
|
OUTL(dev, config, ChipConfig);
|
|
}
|
|
|
|
/* Function: ns8382x_send
|
|
* Description: transmits a packet and waits for completion or timeout.
|
|
* Returns: void. */
|
|
static int
|
|
ns8382x_send(struct eth_device *dev, volatile void *packet, int length)
|
|
{
|
|
u32 i, status = 0;
|
|
vu_long tx_stat = 0;
|
|
|
|
/* Stop the transmitter */
|
|
OUTL(dev, TxOff, ChipCmd);
|
|
#ifdef NS8382X_DEBUG
|
|
printf("ns8382x_send: sending %d bytes\n", (int)length);
|
|
#endif
|
|
|
|
/* set the transmit buffer descriptor and enable Transmit State Machine */
|
|
txd.link = cpu_to_le32(0x0);
|
|
txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet));
|
|
txd.extsts = cpu_to_le32(0x0);
|
|
txd.cmdsts = cpu_to_le32(DescOwn | length);
|
|
|
|
/* load Transmit Descriptor Register */
|
|
OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
|
|
#ifdef NS8382X_DEBUG
|
|
printf("ns8382x_send: TX descriptor register loaded with: %#08X\n",
|
|
INL(dev, TxRingPtr));
|
|
printf("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n",
|
|
le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
|
|
le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
|
|
#endif
|
|
/* restart the transmitter */
|
|
OUTL(dev, TxOn, ChipCmd);
|
|
|
|
for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
|
|
if (i >= TOUT_LOOP) {
|
|
printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
|
|
dev->name, tx_stat);
|
|
goto Done;
|
|
}
|
|
}
|
|
|
|
if (!(tx_stat & DescPktOK)) {
|
|
printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
|
|
goto Done;
|
|
}
|
|
#ifdef NS8382X_DEBUG
|
|
printf("ns8382x_send: tx_stat: %#08X\n", tx_stat);
|
|
#endif
|
|
|
|
status = 1;
|
|
Done:
|
|
return status;
|
|
}
|
|
|
|
/* Function: ns8382x_poll
|
|
* Description: checks for a received packet and returns it if found.
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
* Returns: 1 if packet was received.
|
|
* 0 if no packet was received.
|
|
* Side effects:
|
|
* Returns (copies) the packet to the array dev->packet.
|
|
* Returns the length of the packet.
|
|
*/
|
|
|
|
static int
|
|
ns8382x_poll(struct eth_device *dev)
|
|
{
|
|
int retstat = 0;
|
|
int length = 0;
|
|
vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
|
|
|
|
if (!(rx_status & (u32) DescOwn))
|
|
return retstat;
|
|
#ifdef NS8382X_DEBUG
|
|
printf("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n",
|
|
cur_rx, rx_status);
|
|
#endif
|
|
length = (rx_status & DSIZE) - CRC_SIZE;
|
|
|
|
if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
|
|
/* corrupted packet received */
|
|
printf("ns8382x_poll: Corrupted packet, status:%lx\n", rx_status);
|
|
retstat = 0;
|
|
} else {
|
|
/* give packet to higher level routine */
|
|
NetReceive((rxb + cur_rx * RX_BUF_SIZE), length);
|
|
retstat = 1;
|
|
}
|
|
|
|
/* return the descriptor and buffer to receive ring */
|
|
rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
|
|
rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
|
|
|
|
if (++cur_rx == NUM_RX_DESC)
|
|
cur_rx = 0;
|
|
|
|
/* re-enable the potentially idle receive state machine */
|
|
OUTL(dev, RxOn, ChipCmd);
|
|
|
|
return retstat;
|
|
}
|
|
|
|
/* Function: ns8382x_disable
|
|
* Description: Turns off interrupts and stops Tx and Rx engines
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
* Returns: void.
|
|
*/
|
|
|
|
static void
|
|
ns8382x_disable(struct eth_device *dev)
|
|
{
|
|
/* Disable interrupts using the mask. */
|
|
OUTL(dev, 0, IntrMask);
|
|
OUTL(dev, 0, IntrEnable);
|
|
|
|
/* Stop the chip's Tx and Rx processes. */
|
|
OUTL(dev, (RxOff | TxOff), ChipCmd);
|
|
|
|
/* Restore PME enable bit */
|
|
OUTL(dev, SavedClkRun, ClkRun);
|
|
}
|