9973e3c614
This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
169 lines
4.2 KiB
C
169 lines
4.2 KiB
C
/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/immap.h>
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int checkboard (void) {
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puts ("Board: iDMR\n");
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return 0;
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};
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phys_size_t initdram (int board_type) {
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int i;
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/*
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* After reset, CS0 is configured to cover entire address space. We
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* need to configure it to its proper values, so that writes to
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* CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do
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* now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
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*/
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/* Flash chipselect, CS0 */
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/* ;CSAR0: Flash at 0xFF800000 */
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mbar_writeShort(0x0080, 0xFF80);
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/* CSCR0: Flash 6 waits, 16bit */
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mbar_writeShort(0x008A, 0x1980);
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/* CSMR0: Flash 8MB, R/W, valid */
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mbar_writeLong(0x0084, 0x007F0001);
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/*
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* SDRAM configuration proper
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*/
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/*
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* Address/Data Pin Assignment Reg.: enable address lines 23-21; do
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* not enable data pins D[15:0], as we have 16 bit port to SDRAM
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*/
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mbar_writeByte(MCF_GPIO_PAR_AD,
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MCF_GPIO_AD_ADDR23 |
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MCF_GPIO_AD_ADDR22 |
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MCF_GPIO_AD_ADDR21);
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/* No need to configure BS pins - reset values are OK */
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/* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
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mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
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/* SDRAM Control Pin Assignment Reg. */
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mbar_writeByte(MCF_GPIO_PAR_SDRAM,
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MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
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MCF_GPIO_SDRAM_SDWE |
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MCF_GPIO_SDRAM_SCAS |
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MCF_GPIO_SDRAM_SRAS |
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MCF_GPIO_SDRAM_SCKE |
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MCF_GPIO_SDRAM_SDCS_01);
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/*
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* Wait 100us. We run the bus at 50Mhz, one cycle is 20ns. So 5
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* iterations will do, but we do 10 just to be safe.
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*/
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for (i = 0; i < 10; ++i)
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asm(" nop");
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/* 1. Initialize DRAM Control Register: DCR */
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mbar_writeShort(MCF_SDRAMC_DCR,
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MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */
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MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */
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/*
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* 2. Initialize DACR0
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*
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* CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
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* CBM: cmd at A20, bank select bits 21 and up
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* PS: 16 bit
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*/
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mbar_writeLong(MCF_SDRAMC_DACR0,
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MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
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MCF_SDRAMC_DACRn_BA(0x00) |
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MCF_SDRAMC_DACRn_CASL(0x03) |
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MCF_SDRAMC_DACRn_CBM(0x03) |
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MCF_SDRAMC_DACRn_PS(0x03));
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/* Initialize DMR0 */
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mbar_writeLong(MCF_SDRAMC_DMR0,
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MCF_SDRAMC_DMRn_BAM_16M |
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MCF_SDRAMC_DMRn_V);
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/* 3. Set IP bit in DACR to initiate PALL command */
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mbar_writeLong(MCF_SDRAMC_DACR0,
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mbar_readLong(MCF_SDRAMC_DACR0) |
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MCF_SDRAMC_DACRn_IP);
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/* Write to this block to initiate precharge */
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*(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5;
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/*
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* Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
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* wait a wee longer, just to be safe.
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*/
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for (i = 0; i < 5; ++i)
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asm(" nop");
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/* 4. Set RE bit in DACR */
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mbar_writeLong(MCF_SDRAMC_DACR0,
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mbar_readLong(MCF_SDRAMC_DACR0) |
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MCF_SDRAMC_DACRn_RE);
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/*
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* Wait for at least 8 auto refresh cycles to occur, i.e. at least
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* 781 bus cycles.
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*/
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for (i = 0; i < 1000; ++i)
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asm(" nop");
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/* Finish the configuration by issuing the MRS */
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mbar_writeLong(MCF_SDRAMC_DACR0,
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mbar_readLong(MCF_SDRAMC_DACR0) |
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MCF_SDRAMC_DACRn_MRS);
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/*
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* Write to the SDRAM Mode Register A0-A11 = 0x400
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*
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* Write Burst Mode = Programmed Burst Length
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* Op Mode = Standard Op
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* CAS Latency = 3
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* Burst Type = Sequential
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* Burst Length = 1
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*/
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*(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
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return CFG_SDRAM_SIZE * 1024 * 1024;
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};
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int testdram (void) {
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/* TODO: XXX XXX XXX */
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printf ("DRAM test not implemented!\n");
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return (0);
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}
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