35461fe94e
When the board was added, enabling tzc380 was left off by
mistake. The optee was tested with the following configuration
in s2pro
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 6MiB */
+ optee_core@5f800000 {
+ reg = <0x00 0x5f800000 0x00 0x600000>;
+ };
+
+ /* 2MiB */
+ optee_shm@5fe00000 {
+ reg = <0x00 0x5fe00000 0x00 0x200000>;
+ };
+ };
+
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
82 lines
1.2 KiB
C
82 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 Collabora Ltd.
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*
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*/
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#include <hang.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mn_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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struct udevice *dev;
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int ret;
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debug("Normal Boot\n");
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0)
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puts("Failed to find clock node. Check device tree\n");
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}
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int board_early_init_f(void)
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{
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init_uart_clk(3);
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if (IS_ENABLED(CONFIG_NAND_MXS)) {
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init_nand_clk();
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}
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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arch_cpu_init();
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board_early_init_f();
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timer_init();
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ret = spl_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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