u-boot/arch
Lokesh Vutla ccdb7c2255 armv7r: K3: Allow SPL to run only on core 0
Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.

If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.

If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26 22:52:11 -05:00
..
arc emdk->emsdp: Rename board 2018-11-01 23:04:05 +03:00
arm armv7r: K3: Allow SPL to run only on core 0 2018-11-26 22:52:11 -05:00
m68k m68k: ColdFire mcf5441x, add eSDHC support 2018-09-16 00:01:13 +02:00
microblaze arch: types.h: factor out fixed width typedefs to int-ll64.h 2018-09-10 20:48:16 -04:00
mips MIPS: drop asm/const.h 2018-11-20 13:08:15 +01:00
nds32 Drop CONFIG_INIT_CRITICAL 2018-11-26 13:57:31 +08:00
nios2 .gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore 2018-06-18 14:43:12 -04:00
powerpc spl: Add support for passing handoff info to U-Boot proper 2018-11-26 08:25:37 -05:00
riscv riscv: cache: Implement i/dcache [status, enable, disable] 2018-11-26 13:58:01 +08:00
sandbox spl: Add support for passing handoff info to U-Boot proper 2018-11-26 08:25:37 -05:00
sh Kbuild: add LDFLAGS_STANDALONE 2018-11-18 16:02:23 +01:00
x86 cpu: Add DM_FLAG_PRE_RELOC flag to various cpu drivers 2018-11-14 09:16:28 -08:00
xtensa xtensa: use asm-generic/atomic.h 2018-09-25 21:49:18 -04:00
.gitignore
Kconfig test: Add a simple test for bloblist 2018-11-26 08:25:33 -05:00