cdb23792e8
Remove platform CONFIG_SYS_HZ definition for configs A-Z*. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
489 lines
16 KiB
C
489 lines
16 KiB
C
/*
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* (C) Copyright 2000-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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* Derived from ../tqm8xx/tqm8xx.c
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
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#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
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#define CONFIG_SYS_TEXT_BASE 0x40000000
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200 /* console baudrate */
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \
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"run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \
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"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \
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"run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \
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"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \
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"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \
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bootm 400000 \0" \
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"panic_boot=echo No Bootdevice !!! reset\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \
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":${netmask}:${hostname}:${netdev}:off\0" \
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"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \
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hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \
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"console=ttyCPM0,115200\0" \
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"netdev=eth0\0" \
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"contrast=20\0" \
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"silent=1\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
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"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \
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"cp.b 200000 40050000 14000\0"
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#define CONFIG_BOOTCOMMAND \
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"run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
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#define CONFIG_PREBOOT "setenv preboot; saveenv"
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_MISC_INIT_F 1
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#define CONFIG_WATCHDOG 1 /* watchdog enabled */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/*
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* enable I2C and select the hardware/software driver
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
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/*-----------------------------------------------------------------------
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* I2C Configuration
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*/
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#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
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/* List of I2C addresses to be verified by POST */
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#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
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CONFIG_SYS_I2C_RTC_ADDR, \
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}
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#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
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#define CONFIG_SYS_DISCOVER_PHY
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#define CONFIG_MII
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_SNTP
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#ifdef CONFIG_POST
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#define CONFIG_CMD_DIAG
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */
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#define CONFIG_SYS_ALT_MEMTEST 1
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#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */
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#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xFFF00000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0x40000000
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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/*-----------------------------------------------------------------------
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* Dynamic MTD partition support
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*/
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#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \
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"64k(env)," \
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"128k(splash)," \
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"512k(etc)," \
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"64k(hw-info)"
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/*-----------------------------------------------------------------------
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* Hardware Information Block
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*/
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#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
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#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
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#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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*/
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#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF00
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#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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/* KUP4K use both slots, SLOT_A as "primary". */
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#define CONFIG_PCMCIA_SLOT_A 1
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#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
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#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
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#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
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#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
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#define PCMCIA_SOCKETS_NO 2
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#define PCMCIA_MEM_WIN_NO 8
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#define CONFIG_IDE_LED 1 /* LED for ide supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CONFIG_SYS_IDE_MAXBUS 2
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#define CONFIG_SYS_IDE_MAXDEVICE 4
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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/*
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* FLASH timing:
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*/
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \
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OR_SCY_5_CLK | OR_EHTR | OR_BI)
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#define CONFIG_SYS_OR0_REMAP \
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(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_OR0_PRELIM \
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(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_BR0_PRELIM \
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((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
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/*
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* Memory Periodic Timer Prescaler
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*
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* The Divider for PTA (refresh timer) configuration is based on an
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* example SDRAM configuration (64 MBit, one bank). The adjustment to
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* the number of chip selects (NCS) and the actually needed refresh
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* rate is done by setting MPTPR.
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*
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* PTA is calculated from
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* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
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*
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* gclk CPU clock (not bus clock!)
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* Trefresh Refresh cycle * 4 (four word bursts used)
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*
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* 4096 Rows from SDRAM example configuration
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* 1000 factor s -> ms
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* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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* --------------------------------------------
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* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
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*
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* 50 MHz => 50.000.000 / Divider = 98
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* 66 Mhz => 66.000.000 / Divider = 129
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* 80 Mhz => 80.000.000 / Divider = 156
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*/
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#if defined(CONFIG_80MHz)
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#define CONFIG_SYS_MAMR_PTA 156
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#elif defined(CONFIG_66MHz)
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#define CONFIG_SYS_MAMR_PTA 129
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#else /* 50 MHz */
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#define CONFIG_SYS_MAMR_PTA 98
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#endif /*CONFIG_??MHz */
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/*
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* For 16 MBit, refresh rates could be 31.3 us
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* (= 64 ms / 2K = 125 / quad bursts).
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* For a simpler initialization, 15.6 us is used instead.
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*
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* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
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* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
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*/
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#define CONFIG_SYS_MPTPR 0x400
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/*
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* MAMR settings for SDRAM
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*/
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/* 8 column SDRAM */
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#define CONFIG_SYS_MAMR_8COL 0x68802114
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/* 9 column SDRAM */
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#define CONFIG_SYS_MAMR_9COL 0x68904114
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/*
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* Chip Selects
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*/
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#define CONFIG_SYS_OR0
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#define CONFIG_SYS_BR0
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#define CONFIG_SYS_OR1_8COL 0xFF000A00
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#define CONFIG_SYS_BR1_8COL 0x00000081
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#define CONFIG_SYS_OR2_8COL 0xFE000A00
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#define CONFIG_SYS_BR2_8COL 0x01000081
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#define CONFIG_SYS_OR3_8COL 0xFC000A00
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#define CONFIG_SYS_BR3_8COL 0x02000081
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#define CONFIG_SYS_OR1_9COL 0xFE000A00
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#define CONFIG_SYS_BR1_9COL 0x00000081
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#define CONFIG_SYS_OR2_9COL 0xFE000A00
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#define CONFIG_SYS_BR2_9COL 0x02000081
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#define CONFIG_SYS_OR3_9COL 0xFE000A00
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#define CONFIG_SYS_BR3_9COL 0x04000081
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#define CONFIG_SYS_OR4 0xFFFF8926
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#define CONFIG_SYS_BR4 0x90000401
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#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */
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#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */
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#define LATCH_ADDR 0x90000200
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#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
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#define CONFIG_AUTOBOOT_STOP_STR "."
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#define CONFIG_SILENT_CONSOLE 1
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */
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#define CONFIG_VERSION_VARIABLE 1
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#endif /* __CONFIG_H */
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