93cac85d78
building with MTK_AHCI enabled results in implicit declaration and undefined reference of dev_err followed by a segfault of gcc drivers/ata/mtk_ahci.c: In function 'mtk_ahci_parse_property': drivers/ata/mtk_ahci.c:65:4: warning: implicit declaration of function 'dev_err' drivers/ata/mtk_ahci.c:65: undefined reference to `dev_err' in function `mtk_ahci_probe': drivers/ata/mtk_ahci.c:92: undefined reference to `dev_err' Segmentation fault fix this by adding the dm/device_compat.h to includes Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
132 lines
2.8 KiB
C
132 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* MTK SATA platform driver
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*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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* Author: Frank Wunderlich <frank-w@public-files.de>
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*/
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#include <common.h>
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#include <ahci.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/of_access.h>
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#include <generic-phy.h>
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#include <linux/err.h>
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#include <regmap.h>
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#include <reset.h>
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#include <sata.h>
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#include <scsi.h>
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#include <syscon.h>
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#include <dm/device_compat.h>
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#define SYS_CFG 0x14
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#define SYS_CFG_SATA_MSK GENMASK(31, 30)
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#define SYS_CFG_SATA_EN BIT(31)
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struct mtk_ahci_priv {
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void *base;
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struct ahci_uc_priv ahci_priv;
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struct regmap *mode;
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struct reset_ctl_bulk rst_bulk;
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};
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static int mtk_ahci_bind(struct udevice *dev)
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{
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struct udevice *scsi_dev;
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return ahci_bind_scsi(dev, &scsi_dev);
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}
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static int mtk_ahci_of_to_plat(struct udevice *dev)
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{
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struct mtk_ahci_priv *priv = dev_get_priv(dev);
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priv->base = devfdt_remap_addr_index(dev, 0);
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return 0;
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}
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static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv,
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struct udevice *dev)
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{
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struct mtk_ahci_priv *plat = dev_get_priv(dev);
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const void *fdt = gd->fdt_blob;
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/* enable SATA function if needed */
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if (fdt_get_property(fdt, dev_of_offset(dev),
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"mediatek,phy-mode", NULL)) {
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plat->mode = syscon_regmap_lookup_by_phandle(dev,
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"mediatek,phy-mode");
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if (IS_ERR(plat->mode)) {
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dev_err(dev, "missing phy-mode phandle\n");
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return PTR_ERR(plat->mode);
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}
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regmap_update_bits(plat->mode, SYS_CFG,
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SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN);
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}
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ofnode_read_u32(dev_ofnode(dev), "ports-implemented",
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&hpriv->port_map);
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return 0;
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}
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static int mtk_ahci_probe(struct udevice *dev)
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{
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struct mtk_ahci_priv *priv = dev_get_priv(dev);
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int ret;
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struct phy phy;
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ret = mtk_ahci_parse_property(&priv->ahci_priv, dev);
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if (ret)
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return ret;
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ret = reset_get_bulk(dev, &priv->rst_bulk);
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if (!ret) {
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reset_assert_bulk(&priv->rst_bulk);
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reset_deassert_bulk(&priv->rst_bulk);
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} else {
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dev_err(dev, "Failed to get reset: %d\n", ret);
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}
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ret = generic_phy_get_by_name(dev, "sata-phy", &phy);
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if (ret) {
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pr_err("can't get the phy from DT\n");
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return ret;
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}
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ret = generic_phy_init(&phy);
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if (ret) {
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pr_err("unable to initialize the sata phy\n");
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return ret;
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}
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ret = generic_phy_power_on(&phy);
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if (ret) {
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pr_err("unable to power on the sata phy\n");
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return ret;
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}
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return ahci_probe_scsi(dev, (ulong)priv->base);
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}
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static const struct udevice_id mtk_ahci_ids[] = {
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{ .compatible = "mediatek,mtk-ahci" },
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{ }
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};
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U_BOOT_DRIVER(mtk_ahci) = {
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.name = "mtk_ahci",
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.id = UCLASS_AHCI,
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.of_match = mtk_ahci_ids,
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.bind = mtk_ahci_bind,
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.of_to_plat = mtk_ahci_of_to_plat,
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.ops = &scsi_ops,
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.probe = mtk_ahci_probe,
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.priv_auto = sizeof(struct mtk_ahci_priv),
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};
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