315 lines
9.8 KiB
C
315 lines
9.8 KiB
C
/*
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* (C) Copyright 2007 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <mpc512x.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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#endif
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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#define CSAW_START(start) ((start) & 0xFFFF0000)
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#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
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long int fixed_sdram(void);
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int board_early_init_f (void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 lpcaw;
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/*
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* Initialize Local Window for the CPLD registers access (CS2 selects
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* the CPLD chip)
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*/
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im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
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CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
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im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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lpcaw = im->sysconf.lpcs2aw;
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__asm__ __volatile__ ("isync");
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/*
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* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
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*
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* Without this the flash identification routine fails, as it needs to issue
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* write commands in order to establish the device ID.
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*/
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#ifdef CONFIG_ADS5121_REV2
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*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
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#else
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if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
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*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
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} else {
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/* running from Backup flash */
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*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
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}
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#endif
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/*
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* Configure Flash Speed
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*/
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*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
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if (SVR_MJREV (im->sysconf.spridr) >= 2) {
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*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
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}
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/*
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* Enable clocks
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*/
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im->clk.sccr[0] = SCCR1_CLOCKS_EN;
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im->clk.sccr[1] = SCCR2_CLOCKS_EN;
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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u32 msize = 0;
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msize = fixed_sdram ();
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return msize;
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}
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/*
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* fixed sdram init -- the board doesn't use memory modules that have serial presence
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* detect or similar mechanism for discovery of the DRAM settings
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*/
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long int fixed_sdram (void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2 (msize);
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u32 i;
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/* Initialize IO Control */
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im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
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/* Initialize DDR Local Window */
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im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
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im->sysconf.ddrlaw.ar = msize_log2 - 1;
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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i = im->sysconf.ddrlaw.ar;
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__asm__ __volatile__ ("isync");
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/* Enable DDR */
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im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
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/* Initialize DDR Priority Manager */
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im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
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im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
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im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
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im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
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im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
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im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
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im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
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im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
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im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
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im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
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im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
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im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
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im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
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im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
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im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
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im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
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im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
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im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
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im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
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im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
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im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
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im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
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im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
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/* Initialize MDDRC */
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im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
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im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
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im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
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im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
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/* Initialize DDR */
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for (i = 0; i < 10; i++)
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
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im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
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/* Start MDDRC */
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im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
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im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
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return msize;
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}
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int misc_init_r(void)
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{
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u8 tmp_val;
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extern int ads5121_diu_init(void);
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/* Using this for DIU init before the driver in linux takes over
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* Enable the TFP410 Encoder (I2C address 0x38)
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*/
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i2c_set_bus_num(2);
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tmp_val = 0xBF;
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i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
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/* Verify if enabled */
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tmp_val = 0;
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i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
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debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
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tmp_val = 0x10;
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i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
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/* Verify if enabled */
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tmp_val = 0;
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i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
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debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
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#ifdef CONFIG_FSL_DIU_FB
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#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
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ads5121_diu_init();
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#endif
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#endif
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return 0;
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}
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static iopin_t ioregs_init[] = {
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/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
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{
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IOCTL_SPDIF_TXCLK, 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* Set highest Slew on 9 PATA pins */
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{
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IOCTL_PATA_CE1, 9, 1,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
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{
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IOCTL_PSC0_0, 15, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=SPDIF_TXCLK */
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{
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IOCTL_LPC_CS1, 1, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
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{
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IOCTL_I2C1_SCL, 2, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU CLK */
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{
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IOCTL_PSC6_0, 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU_HSYNC */
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{
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IOCTL_PSC6_1, 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
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{
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IOCTL_PSC6_4, 26, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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}
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};
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int checkboard (void)
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{
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ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
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uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
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printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
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brd_rev, cpld_rev);
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/* initialize function mux & slew rate IO inter alia on IO Pins */
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iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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