39fa17718f
Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_WR_LOW to CFG_LPC32XX_NAND_MLC_WR_LOW Signed-off-by: Tom Rini <trini@konsulko.com>
73 lines
1.5 KiB
C
73 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* WORK Microwave work_92105 board configuration file
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*
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* (C) Copyright 2014 DENX Software Engineering GmbH
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* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
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*/
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#ifndef __CONFIG_WORK_92105_H__
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#define __CONFIG_WORK_92105_H__
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/* SoC and board defines */
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#include <linux/sizes.h>
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#include <asm/arch/cpu.h>
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/*
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* Memory configurations
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*/
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#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
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#define CFG_SYS_SDRAM_SIZE SZ_128M
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/*
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* U-Boot General Configurations
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*/
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/*
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* NAND chip timings for FIXME: which one?
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*/
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#define CFG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
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#define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
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#define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818
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#define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000
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#define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545
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#define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000
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#define CFG_LPC32XX_NAND_MLC_WR_LOW 83333333
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/*
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* NAND
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*/
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/* driver configuration */
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#define CFG_SYS_MAX_NAND_CHIPS 1
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#define CFG_SYS_NAND_BASE MLC_NAND_BASE
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/*
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* GPIO
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*/
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/*
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* Environment
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*/
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/*
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* SPL
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*/
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/* SPL will be executed at offset 0 */
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/* SPL will use SRAM as stack */
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/* Use the framework and generic lib */
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/* SPL will use serial */
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/* SPL will load U-Boot from NAND offset 0x40000 */
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/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
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#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
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#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
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/*
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* Include SoC specific configuration
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*/
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#include <asm/arch/config.h>
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#endif /* __CONFIG_WORK_92105_H__*/
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