85056932f2
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
42 lines
959 B
C
42 lines
959 B
C
/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pnp_def.h>
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#define WINBOND_ENTRY_KEY 0x87
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#define WINBOND_EXIT_KEY 0xaa
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/* Enable configuration: pass entry key '0x87' into index port dev twice */
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static void pnp_enter_conf_state(u16 dev)
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{
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u16 port = dev >> 8;
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outb(WINBOND_ENTRY_KEY, port);
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outb(WINBOND_ENTRY_KEY, port);
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}
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/* Disable configuration: pass exit key '0xAA' into index port dev */
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static void pnp_exit_conf_state(u16 dev)
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{
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u16 port = dev >> 8;
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outb(WINBOND_EXIT_KEY, port);
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}
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/* Bring up early serial debugging output before the RAM is initialized */
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void winbond_enable_serial(uint dev, uint iobase, uint irq)
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{
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_irq(dev, PNP_IDX_IRQ0, irq);
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pnp_set_enable(dev, 1);
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pnp_exit_conf_state(dev);
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}
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