84488fc693
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for instruction and data caches sizes, respectively: CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Also, get rid of the hardcoded value in icache_disable(). Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
90 lines
1.5 KiB
C
90 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/asm.h>
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#include <asm/cache.h>
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static void __invalidate_icache(ulong addr, ulong size)
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{
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if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
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for (int i = 0; i < size; i += 4) {
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asm volatile (
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"wic %0, r0;"
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"nop;"
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:
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: "r" (addr + i)
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: "memory");
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}
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}
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}
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static void __flush_dcache(ulong addr, ulong size)
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{
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if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
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for (int i = 0; i < size; i += 4) {
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asm volatile (
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"wdc.flush %0, r0;"
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"nop;"
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:
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: "r" (addr + i)
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: "memory");
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}
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}
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}
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int dcache_status(void)
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{
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int i = 0;
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int mask = 0x80;
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__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
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/* i&=0x80 */
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__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
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return i;
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}
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int icache_status(void)
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{
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int i = 0;
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int mask = 0x20;
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__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
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/* i&=0x20 */
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__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
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return i;
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}
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void icache_enable(void)
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{
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MSRSET(0x20);
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}
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void icache_disable(void)
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{
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__invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
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MSRCLR(0x20);
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}
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void dcache_enable(void)
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{
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MSRSET(0x80);
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}
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void dcache_disable(void)
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{
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__flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
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MSRCLR(0x80);
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}
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void flush_cache(ulong addr, ulong size)
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{
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__invalidate_icache(addr, size);
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__flush_dcache(addr, size);
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}
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