8b0044ff59
New QorIQ p1020 based board support from Arcturus Networks Inc. http://www.arcturusnetworks.com/products/ucp1020/ Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com> [York Sun: remove patman tags from commit message] Reviewed-by: York Sun <yorksun@freescale.com>
102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
/*
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* Copyright 2013-2015 Arcturus Networks, Inc
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* http://www.arcturusnetworks.com/products/ucp1020/
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* based on board/freescale/p1_p2_rdb_pc/tlb.c
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* original copyright follows:
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
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0, 0, BOOKE_PAGESZ_4K, 1),
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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#ifndef CONFIG_SPL_BUILD
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/* W**G* - Flash/promjet, localbus */
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
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0, 2, BOOKE_PAGESZ_64M, 1),
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#ifdef CONFIG_PCI
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/* *I*G* - PCI memory 1.5G */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 3, BOOKE_PAGESZ_1G, 1),
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/* *I*G* - PCI I/O effective: 192K */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 4, BOOKE_PAGESZ_256K, 1),
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#endif
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#ifdef CONFIG_VSC7385_ENET
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/* *I*G - VSC7385 Switch */
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SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 5, BOOKE_PAGESZ_1M, 1),
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#endif
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#endif /* not SPL */
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#ifdef CONFIG_SYS_NAND_BASE
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/* *I*G - NAND */
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 7, BOOKE_PAGESZ_1M, 1),
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#endif
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#if defined(CONFIG_SYS_RAMBOOT) || \
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(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
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/* *I*G - eSDHC/eSPI/NAND boot */
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 8, BOOKE_PAGESZ_1G, 1),
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#endif /* RAMBOOT/SPL */
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#ifdef CONFIG_SYS_INIT_L2_ADDR
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/* *I*G - L2SRAM */
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
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0, 11, BOOKE_PAGESZ_256K, 1),
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#if CONFIG_SYS_L2_SIZE >= (256 << 10)
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
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CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 12, BOOKE_PAGESZ_256K, 1)
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#endif
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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