1cca8ba9ec
To be compatible with old u-boot used by lots of MT7621 devices, the u-boot needs to boot-up MT7621's all cores, and all VPES of each core. This patch adds asm/mipsmtregs.h from linux kernel which is need for boot-up VPEs. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
143 lines
4.3 KiB
C
143 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* MT regs definitions, follows on from mipsregs.h
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* Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
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* Elizabeth Clarke et. al.
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*
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*/
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#ifndef _ASM_MIPSMTREGS_H
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#define _ASM_MIPSMTREGS_H
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#include <asm/mipsregs.h>
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/*
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* Macros for use in assembly language code
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*/
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#define CP0_MVPCONTROL $0, 1
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#define CP0_MVPCONF0 $0, 2
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#define CP0_MVPCONF1 $0, 3
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#define CP0_VPECONTROL $1, 1
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#define CP0_VPECONF0 $1, 2
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#define CP0_VPECONF1 $1, 3
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#define CP0_YQMASK $1, 4
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#define CP0_VPESCHEDULE $1, 5
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#define CP0_VPESCHEFBK $1, 6
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#define CP0_TCSTATUS $2, 1
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#define CP0_TCBIND $2, 2
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#define CP0_TCRESTART $2, 3
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#define CP0_TCHALT $2, 4
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#define CP0_TCCONTEXT $2, 5
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#define CP0_TCSCHEDULE $2, 6
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#define CP0_TCSCHEFBK $2, 7
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#define CP0_SRSCONF0 $6, 1
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#define CP0_SRSCONF1 $6, 2
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#define CP0_SRSCONF2 $6, 3
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#define CP0_SRSCONF3 $6, 4
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#define CP0_SRSCONF4 $6, 5
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/* MVPControl fields */
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#define MVPCONTROL_EVP (_ULCAST_(1))
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#define MVPCONTROL_VPC_SHIFT 1
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#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
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#define MVPCONTROL_STLB_SHIFT 2
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#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
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/* MVPConf0 fields */
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#define MVPCONF0_PTC_SHIFT 0
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#define MVPCONF0_PTC (_ULCAST_(0xff))
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#define MVPCONF0_PVPE_SHIFT 10
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#define MVPCONF0_PVPE (_ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
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#define MVPCONF0_TCA_SHIFT 15
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#define MVPCONF0_TCA (_ULCAST_(1) << MVPCONF0_TCA_SHIFT)
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#define MVPCONF0_PTLBE_SHIFT 16
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#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
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#define MVPCONF0_TLBS_SHIFT 29
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#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
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#define MVPCONF0_M_SHIFT 31
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#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
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/* config3 fields */
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#define CONFIG3_MT_SHIFT 2
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#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
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/* VPEControl fields (per VPE) */
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#define VPECONTROL_TARGTC (_ULCAST_(0xff))
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#define VPECONTROL_TE_SHIFT 15
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#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
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#define VPECONTROL_EXCPT_SHIFT 16
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#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
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/* Thread Exception Codes for EXCPT field */
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#define THREX_TU 0
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#define THREX_TO 1
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#define THREX_IYQ 2
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#define THREX_GSX 3
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#define THREX_YSCH 4
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#define THREX_GSSCH 5
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#define VPECONTROL_GSI_SHIFT 20
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#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
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#define VPECONTROL_YSI_SHIFT 21
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#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
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/* VPEConf0 fields (per VPE) */
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#define VPECONF0_VPA_SHIFT 0
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#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
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#define VPECONF0_MVP_SHIFT 1
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#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
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#define VPECONF0_XTC_SHIFT 21
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#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
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/* VPEConf1 fields (per VPE) */
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#define VPECONF1_NCP1_SHIFT 0
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#define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
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#define VPECONF1_NCP2_SHIFT 10
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#define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
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#define VPECONF1_NCX_SHIFT 20
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#define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
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/* TCStatus fields (per TC) */
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#define TCSTATUS_TASID (_ULCAST_(0xff))
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#define TCSTATUS_IXMT_SHIFT 10
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#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
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#define TCSTATUS_TKSU_SHIFT 11
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#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
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#define TCSTATUS_A_SHIFT 13
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#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
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#define TCSTATUS_DA_SHIFT 15
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#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
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#define TCSTATUS_DT_SHIFT 20
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#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
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#define TCSTATUS_TDS_SHIFT 21
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#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
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#define TCSTATUS_TSST_SHIFT 22
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#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
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#define TCSTATUS_RNST_SHIFT 23
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#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
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/* Codes for RNST */
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#define TC_RUNNING 0
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#define TC_WAITING 1
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#define TC_YIELDING 2
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#define TC_GATED 3
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#define TCSTATUS_TMX_SHIFT 27
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#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
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/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
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/* TCBind */
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#define TCBIND_CURVPE_SHIFT 0
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#define TCBIND_CURVPE (_ULCAST_(0xf))
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#define TCBIND_CURTC_SHIFT 21
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#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
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/* TCHalt */
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#define TCHALT_H (_ULCAST_(1))
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#endif
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