81e33f4b65
Until now, the SoC selection for the ARCH_MVEBU platforms has been done in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As it needed to get selected for AXP and A38x based boards. This patch now changes this to move the SoC selection to Kconfig. And also uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x. This makes things a bit clearer - especially for new board additions. Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available CONFIG_ARMADA_38X and CONFIG_ARMADA_XP. And CONFIG_DDR3 is removed, as its not referenced anywhere. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
43 lines
930 B
C
43 lines
930 B
C
/*
|
|
* Copyright (C) Marvell International Ltd. and its affiliates
|
|
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
|
*
|
|
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/soc.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define TIMER_LOAD_VAL 0xffffffff
|
|
|
|
static int init_done __attribute__((section(".data"))) = 0;
|
|
|
|
/*
|
|
* Timer initialization
|
|
*/
|
|
int timer_init(void)
|
|
{
|
|
/* Only init the timer once */
|
|
if (init_done)
|
|
return 0;
|
|
init_done = 1;
|
|
|
|
/* load value into timer */
|
|
writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10);
|
|
writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14);
|
|
|
|
#if defined(CONFIG_ARCH_MVEBU)
|
|
/* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */
|
|
setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11));
|
|
#endif
|
|
/* enable timer in auto reload mode */
|
|
setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3);
|
|
|
|
return 0;
|
|
}
|