281e00a3be
* Patch by Sascha Hauer, 28 Jun: - add generic support for Motorola i.MX architecture - add support for mx1ads, mx1fs2 and scb9328 boards * Patches by Marc Leeman, 23 Jul 2004: - Add define for the PCI/Memory Buffer Configuration Register - corrected comments in cpu/mpc824x/cpu_init.c * Add support for multiple serial interfaces (for example to allow modem dial-in / dial-out)
323 lines
7.5 KiB
C
323 lines
7.5 KiB
C
/*
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* board/mx1ads/syncflash.c
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*
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* (c) Copyright 2004
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* Techware Information Technology, Inc.
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* http://www.techware.com.tw/
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*
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* Ming-Len Wu <minglen_wu@techware.com.tw>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*#include <mc9328.h>*/
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#include <asm/arch/imx-regs.h>
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typedef unsigned long * p_u32;
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/* 4Mx16x2 IAM=0 CSD1 */
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* Following Setting is for CSD1 */
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#define SFCTL 0x00221004
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#define reg_SFCTL __REG(SFCTL)
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#define SYNCFLASH_A10 (0x00100000)
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#define CMD_NORMAL (0x81020300) /* Normal Mode */
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#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
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#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
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#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
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#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
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#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
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#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
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/* LCR Command */
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#define LCR_READSTATUS (0x0001C000) /* 0x70 */
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#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
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#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
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#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
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#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
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/* Get Status register */
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u32 SF_SR(void) {
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u32 tmp,tmp1;
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reg_SFCTL = CMD_PROGRAM;
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tmp = __REG(CFG_FLASH_BASE);
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reg_SFCTL = CMD_NORMAL;
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reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
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tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
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return tmp;
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}
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/* check if SyncFlash is ready */
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u8 SF_Ready(void) {
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u32 tmp;
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tmp = SF_SR();
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if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
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printf ("SyncFlash Error code %08x\n",tmp);
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};
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if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
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printf ("SyncFlash Error code %08x\n",tmp);
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};
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if (tmp == 0x00800080) /* Test Bit 7 of SR */
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return 1;
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else
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return 0;
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}
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/* Issue the precharge all command */
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void SF_PrechargeAll(void) {
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u32 tmp;
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reg_SFCTL = CMD_PREC; /* Set Precharge Command */
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tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
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}
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/* set SyncFlash to normal mode */
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void SF_Normal(void) {
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SF_PrechargeAll();
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reg_SFCTL = CMD_NORMAL;
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}
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/* Erase SyncFlash */
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void SF_Erase(u32 RowAddress) {
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u32 tmp;
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reg_SFCTL = CMD_NORMAL;
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tmp = __REG(RowAddress);
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reg_SFCTL = CMD_PREC;
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tmp = __REG(RowAddress);
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reg_SFCTL = CMD_LCR; /* Set LCR mode */
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__REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
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reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
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__REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
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while(!SF_Ready());
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}
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void SF_NvmodeErase(void) {
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SF_PrechargeAll();
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reg_SFCTL = CMD_LCR; /* Set to LCR mode */
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__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
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reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
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__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
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while(!SF_Ready());
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}
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void SF_NvmodeWrite(void) {
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SF_PrechargeAll();
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reg_SFCTL = CMD_LCR; /* Set to LCR mode */
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__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
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reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
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__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
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}
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/****************************************************************************************/
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ulong flash_init(void) {
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int i, j;
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u32 tmp;
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/* Turn on CSD1 for negating RESETSF of SyncFLash */
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reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
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udelay(200);
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reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
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tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
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SF_Normal();
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i = 0;
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flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
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flash_info[i].size = FLASH_BANK_SIZE;
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flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
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memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
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for (j = 0; j < flash_info[i].sector_count; j++) {
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flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
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}
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flash_protect(FLAG_PROTECT_SET,
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CFG_FLASH_BASE,
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CFG_FLASH_BASE + monitor_flash_len - 1,
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&flash_info[0]);
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
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&flash_info[0]);
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return FLASH_BANK_SIZE;
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}
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void flash_print_info (flash_info_t *info) {
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int i;
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switch (info->flash_id & FLASH_VENDMASK) {
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case (FLASH_MAN_MT & FLASH_VENDMASK):
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printf("Micron: ");
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break;
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default:
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printf("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
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printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
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break;
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default:
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printf("Unknown Chip Type\n");
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return;
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break;
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}
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printf(" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf(" Sector Start Addresses: ");
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for (i = 0; i < info->sector_count; i++) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s", info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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}
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/*-----------------------------------------------------------------------*/
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int flash_erase (flash_info_t *info, int s_first, int s_last) {
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int iflag, cflag, prot, sect;
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int rc = ERR_OK;
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/* first look for protection bits */
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if (info->flash_id == FLASH_UNKNOWN)
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return ERR_UNKNOWN_FLASH_TYPE;
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if ((s_first < 0) || (s_first > s_last))
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return ERR_INVAL;
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if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
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return ERR_UNKNOWN_FLASH_VENDOR;
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect])
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prot++;
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}
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if (prot) {
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printf("protected!\n");
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return ERR_PROTECTED;
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}
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/*
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* Disable interrupts which might cause a timeout
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* here. Remember that our exception vectors are
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* at address 0 in the flash, and we don't want a
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* (ticker) exception to happen while the flash
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* chip is in programming mode.
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*/
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cflag = icache_status();
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icache_disable();
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iflag = disable_interrupts();
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
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printf("Erasing sector %2d ... ", sect);
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked();
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SF_NvmodeErase();
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SF_NvmodeWrite();
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SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect));
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SF_Normal();
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printf("ok.\n");
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}
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if (ctrlc())
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printf("User Interrupt!\n");
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if (iflag)
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enable_interrupts();
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if (cflag)
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icache_enable();
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return rc;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash.
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
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int i;
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for(i = 0; i < cnt; i += 4) {
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SF_PrechargeAll();
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reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
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__REG(addr + i) = __REG((u32)src + i);
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while(!SF_Ready());
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}
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SF_Normal();
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return ERR_OK;
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}
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