161 lines
3.8 KiB
C
161 lines
3.8 KiB
C
/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <asm/arch/ixp425.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include "actux1_hw.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_init (void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
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/* Setup GPIO's for PCI INTA */
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GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
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GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
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/* Setup GPIO's for 33MHz clock output */
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
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GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
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*IXP425_GPIO_GPCLKR = 0x011001FF;
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/* CS5: Debug port */
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*IXP425_EXP_CS5 = 0x9d520003;
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/* CS6: HwRel */
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*IXP425_EXP_CS6 = 0x81860001;
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/* CS7: LEDs */
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*IXP425_EXP_CS7 = 0x80900003;
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udelay (533);
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GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
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ACTUX1_LED1 (2);
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ACTUX1_LED2 (2);
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ACTUX1_LED3 (0);
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ACTUX1_LED4 (0);
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ACTUX1_LED5 (0);
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ACTUX1_LED6 (0);
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ACTUX1_LED7 (0);
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ACTUX1_HS (ACTUX1_HS_DCD);
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return 0;
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}
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/*
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* Check Board Identity
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*/
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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puts ("Board: AcTux-1 rev.");
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putc (ACTUX1_BOARDREL + 'A' - 1);
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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return (0);
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}
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/*************************************************************************
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* get_board_rev() - setup to pass kernel board revision information
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* 0 = reserved
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* 1 = Rev. A
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* 2 = Rev. B
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*************************************************************************/
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u32 get_board_rev (void)
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{
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return ACTUX1_BOARDREL;
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}
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return (0);
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}
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#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
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extern struct pci_controller hose;
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extern void pci_ixp_init (struct pci_controller *hose);
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void pci_init_board (void)
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{
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extern void pci_ixp_init (struct pci_controller *hose);
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pci_ixp_init (&hose);
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}
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#endif
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void reset_phy (void)
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{
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u16 id1, id2;
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/* initialize the PHY */
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miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
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miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR1, &id1);
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miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR2, &id2);
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id2 &= 0xFFF0; /* mask out revision bits */
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if (id1 == 0x13 && id2 == 0x78e0) {
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/*
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* LXT971/LXT972 PHY: set LED outputs:
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* LED1(green) = Link/ACT,
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* LED2 (unused) = LINK,
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* LED3(red) = Coll
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*/
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miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
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} else if (id1 == 0x143 && id2 == 0xbc30) {
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/* BCM5241: default values are OK */
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} else
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printf ("unknown ethernet PHY ID: %x %x\n", id1, id2);
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}
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