baf37f06c5
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.
Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.
Tested on:
- A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
with and without an L2 cache.
- QEMU.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
126 lines
3.3 KiB
C
126 lines
3.3 KiB
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <msc01.h>
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#include <pci.h>
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#include <pci_msc01.h>
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#include <asm/io.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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struct msc01_pci_controller {
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struct pci_controller hose;
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void *base;
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};
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static inline struct msc01_pci_controller *
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hose_to_msc01(struct pci_controller *hose)
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{
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return container_of(hose, struct msc01_pci_controller, hose);
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}
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static int msc01_config_access(struct msc01_pci_controller *msc01,
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unsigned char access_type, pci_dev_t bdf,
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int where, u32 *data)
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{
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const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
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void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
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void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
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unsigned int bus = PCI_BUS(bdf);
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unsigned int dev = PCI_DEV(bdf);
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unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
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/* clear abort status */
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__raw_writel(aborts, intstat);
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/* setup address */
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__raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
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(dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
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(devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
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((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
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msc01->base + MSC01_PCI_CFGADDR_OFS);
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/* perform access */
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if (access_type == PCI_ACCESS_WRITE)
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__raw_writel(*data, cfgdata);
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else
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*data = __raw_readl(cfgdata);
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/* check for aborts */
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if (__raw_readl(intstat) & aborts) {
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/* clear abort status */
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__raw_writel(aborts, intstat);
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return -1;
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}
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return 0;
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}
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static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
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int where, u32 *value)
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{
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struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
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*value = 0xffffffff;
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return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
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}
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static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
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int where, u32 value)
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{
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struct msc01_pci_controller *gt = hose_to_msc01(hose);
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u32 data = value;
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return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
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}
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void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
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unsigned long sys_size, unsigned long mem_bus,
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unsigned long mem_phys, unsigned long mem_size,
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unsigned long io_bus, unsigned long io_phys,
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unsigned long io_size)
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{
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static struct msc01_pci_controller global_msc01;
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struct msc01_pci_controller *msc01;
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struct pci_controller *hose;
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msc01 = &global_msc01;
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msc01->base = base;
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hose = &msc01->hose;
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* System memory space */
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pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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/* PCI memory space */
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pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
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PCI_REGION_IO);
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hose->region_count = 3;
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pci_set_ops(hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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msc01_read_config_dword,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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msc01_write_config_dword);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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}
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