587 lines
24 KiB
C
587 lines
24 KiB
C
/*
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* kilauea.h - configuration for AMCC Kilauea (405EX)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_KILAUEA 1 /* Board is Kilauea */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_405EX 1 /* Specifc 405EX support*/
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#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME kilauea
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_BOARD_EMAC_COUNT
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_BASE 0xFC000000
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#define CFG_NAND_ADDR 0xF8000000
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#define CFG_FPGA_BASE 0xF0000000
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#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
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/*-----------------------------------------------------------------------
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* Initial RAM & Stack Pointer Configuration Options
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*
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* There are traditionally three options for the primordial
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* (i.e. initial) stack usage on the 405-series:
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*
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* 1) On-chip Memory (OCM) (i.e. SRAM)
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* 2) Data cache
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* 3) SDRAM
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*
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* For the 405EX(r), there is no OCM, so we are left with (2) or (3)
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* the latter of which is less than desireable since it requires
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* setting up the SDRAM and ECC in assembly code.
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*
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* To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
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* select on the External Bus Controller (EBC) and then select a
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* value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
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* physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
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* select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
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* physical SDRAM to use (3).
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*-----------------------------------------------------------------------*/
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#define CFG_INIT_DCACHE_CS 4
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#if defined(CFG_INIT_DCACHE_CS)
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#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
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#else
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#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */
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#endif /* defined(CFG_INIT_DCACHE_CS) */
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#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/*
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* If the data cache is being used for the primordial stack and global
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* data area, the POST word must be placed somewhere else. The General
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* Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
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* its compare and mask register contents across reset, so it is used
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* for the POST word.
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*/
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#if defined(CFG_INIT_DCACHE_CS)
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# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
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#else
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# define CFG_INIT_EXTRA_SIZE 16
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# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
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# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
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# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR
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#endif /* defined(CFG_INIT_DCACHE_CS) */
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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/* define this if you want console on UART1 */
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#undef CONFIG_UART1_CONSOLE
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 4k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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* On 405EX the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from location 0xfffff000...0xffffffff the
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* NAND controller cannot be accessed since it is attached to CS0 too.
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*/
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#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
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#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
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#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
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/*
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* Now the NAND chip has to be defined (no autodetection used!)
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*/
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#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
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#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
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#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
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#define CFG_NAND_ECCSIZE 256
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#define CFG_NAND_ECCBYTES 3
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#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
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#define CFG_NAND_OOBSIZE 16
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#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
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#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
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#ifdef CONFIG_ENV_IS_IN_NAND
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/*
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* For NAND booting the environment is embedded in the U-Boot image. Please take
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* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
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*/
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#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
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#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
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#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_SDRAM (256) /* 256MB */
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/*
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* CONFIG_PPC4xx_DDR_AUTOCALIBRATION
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*
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* Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
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* SDRAM Controller DDR autocalibration values and takes a lot longer
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* to run than Method_B.
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* (See the Method_A and Method_B algorithm discription in the file:
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* cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
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* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
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*
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* DDR Autocalibration Method_B is the default.
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*/
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#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
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#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
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#undef CONFIG_PPC4xx_DDR_METHOD_A
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#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
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/* DDR1/2 SDRAM Device Control Register Data Values */
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#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \
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SDRAM_RXBAS_SDSZ_256MB | \
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SDRAM_RXBAS_SDAM_MODE7 | \
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SDRAM_RXBAS_SDBE_ENABLE)
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#define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
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#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
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#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
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#define CFG_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
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SDRAM_MCOPT1_8_BANKS | \
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SDRAM_MCOPT1_DDR2_TYPE | \
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SDRAM_MCOPT1_QDEP | \
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SDRAM_MCOPT1_DCOO_DISABLED)
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#define CFG_SDRAM0_MCOPT2 0x00000000
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#define CFG_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
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SDRAM_MODT_EB0R_ENABLE)
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#define CFG_SDRAM0_MODT1 0x00000000
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#define CFG_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
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SDRAM_CODT_CKLZ_36OHM | \
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SDRAM_CODT_DQS_1_8_V_DDR2 | \
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SDRAM_CODT_IO_NMODE)
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#define CFG_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
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#define CFG_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(80) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
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#define CFG_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(3) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
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#define CFG_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
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#define CFG_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
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SDRAM_INITPLR_IMA_ENCODE(0))
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#define CFG_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
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JEDEC_MA_EMR_RTT_75OHM))
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#define CFG_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
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JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
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JEDEC_MA_MR_BLEN_4 | \
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JEDEC_MA_MR_DLL_RESET))
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#define CFG_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(3) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
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SDRAM_INITPLR_IBA_ENCODE(0x0) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
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#define CFG_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CFG_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CFG_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CFG_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CFG_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
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JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
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JEDEC_MA_MR_BLEN_4))
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#define CFG_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
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JEDEC_MA_EMR_RDQS_DISABLE | \
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JEDEC_MA_EMR_DQS_DISABLE | \
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JEDEC_MA_EMR_RTT_DISABLED | \
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JEDEC_MA_EMR_ODS_NORMAL))
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#define CFG_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
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JEDEC_MA_EMR_RDQS_DISABLE | \
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JEDEC_MA_EMR_DQS_DISABLE | \
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JEDEC_MA_EMR_RTT_DISABLED | \
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JEDEC_MA_EMR_ODS_NORMAL))
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#define CFG_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
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#define CFG_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
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#define CFG_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
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SDRAM_RQDC_RQFD_ENCODE(56))
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#define CFG_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
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#define CFG_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
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#define CFG_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
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SDRAM_DLCR_DLCS_CONT_DONE | \
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SDRAM_DLCR_DLCV_ENCODE(165))
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#define CFG_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
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#define CFG_SDRAM0_WRDTR 0x00000000
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#define CFG_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
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SDRAM_SDTR1_RTW_2_CLK | \
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SDRAM_SDTR1_RTRO_1_CLK)
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#define CFG_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
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SDRAM_SDTR2_WTR_2_CLK | \
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SDRAM_SDTR2_XSNR_32_CLK | \
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SDRAM_SDTR2_WPC_4_CLK | \
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SDRAM_SDTR2_RPC_2_CLK | \
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SDRAM_SDTR2_RP_3_CLK | \
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SDRAM_SDTR2_RRD_2_CLK)
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#define CFG_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
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SDRAM_SDTR3_RC_ENCODE(11) | \
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SDRAM_SDTR3_XCS | \
|
|
SDRAM_SDTR3_RFC_ENCODE(26))
|
|
#define CFG_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
|
|
SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
|
|
SDRAM_MMODE_BLEN_4)
|
|
#define CFG_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
|
|
SDRAM_MEMODE_RTT_75OHM)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* I2C
|
|
*----------------------------------------------------------------------*/
|
|
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
|
|
|
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
|
|
#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
|
|
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
|
|
|
/* Standard DTT sensor configuration */
|
|
#define CONFIG_DTT_DS1775 1
|
|
#define CONFIG_DTT_SENSORS { 0 }
|
|
#define CFG_I2C_DTT_ADDR 0x48
|
|
|
|
/* RTC configuration */
|
|
#define CONFIG_RTC_DS1338 1
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|
#define CFG_I2C_RTC_ADDR 0x68
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Ethernet
|
|
*----------------------------------------------------------------------*/
|
|
#define CONFIG_M88E1111_PHY 1
|
|
#define CONFIG_IBM_EMAC4_V4 1
|
|
#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
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|
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
|
|
|
|
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
|
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
|
|
|
#define CONFIG_HAS_ETH0 1
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|
|
|
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
|
|
#define CONFIG_PHY1_ADDR 2
|
|
|
|
/* Debug messages for the DDR autocalibration */
|
|
#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
|
|
|
|
/*
|
|
* Default environment variables
|
|
*/
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
CONFIG_AMCC_DEF_ENV \
|
|
CONFIG_AMCC_DEF_ENV_POWERPC \
|
|
CONFIG_AMCC_DEF_ENV_PPC_OLD \
|
|
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
|
CONFIG_AMCC_DEF_ENV_NAND_UPD \
|
|
"logversion=2\0" \
|
|
"kernel_addr=fc000000\0" \
|
|
"fdt_addr=fc1e0000\0" \
|
|
"ramdisk_addr=fc200000\0" \
|
|
"pciconfighost=1\0" \
|
|
"pcie_mode=RP:RP\0" \
|
|
""
|
|
|
|
/*
|
|
* Commands additional to the ones defined in amcc-common.h
|
|
*/
|
|
#define CONFIG_CMD_DATE
|
|
#define CONFIG_CMD_LOG
|
|
#define CONFIG_CMD_NAND
|
|
#define CONFIG_CMD_PCI
|
|
#define CONFIG_CMD_SNTP
|
|
|
|
/* POST support */
|
|
#define CONFIG_POST (CFG_POST_CACHE | \
|
|
CFG_POST_CPU | \
|
|
CFG_POST_ETHER | \
|
|
CFG_POST_I2C | \
|
|
CFG_POST_MEMORY | \
|
|
CFG_POST_UART)
|
|
|
|
/* Define here the base-addresses of the UARTs to test in POST */
|
|
#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
|
|
|
|
#define CONFIG_LOGBUFFER
|
|
#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
|
|
|
|
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PCI stuff
|
|
*----------------------------------------------------------------------*/
|
|
#define CONFIG_PCI /* include pci support */
|
|
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
|
|
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
|
|
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PCIe stuff
|
|
*----------------------------------------------------------------------*/
|
|
#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
|
|
#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
|
|
|
|
#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
|
|
#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
|
|
#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
|
|
|
|
#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
|
|
#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
|
|
#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
|
|
|
|
#define CFG_PCIE0_UTLBASE 0xef502000
|
|
#define CFG_PCIE1_UTLBASE 0xef503000
|
|
|
|
/* base address of inbound PCIe window */
|
|
#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* External Bus Controller (EBC) Setup
|
|
*----------------------------------------------------------------------*/
|
|
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
|
/* booting from NAND, so NAND chips select has to be on CS 0 */
|
|
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
|
|
|
|
/* Memory Bank 1 (NOR-FLASH) initialization */
|
|
#define CFG_EBC_PB1AP 0x05806500
|
|
#define CFG_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
|
|
|
|
/* Memory Bank 0 (NAND-FLASH) initialization */
|
|
#define CFG_EBC_PB0AP 0x018003c0
|
|
#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1e000)
|
|
#else
|
|
#define CFG_NAND_CS 1 /* NAND chip connected to CSx */
|
|
|
|
/* Memory Bank 0 (NOR-FLASH) initialization */
|
|
#define CFG_EBC_PB0AP 0x05806500
|
|
#define CFG_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
|
|
|
|
/* Memory Bank 1 (NAND-FLASH) initialization */
|
|
#define CFG_EBC_PB1AP 0x018003c0
|
|
#define CFG_EBC_PB1CR (CFG_NAND_ADDR | 0x1e000)
|
|
#endif
|
|
|
|
/* Memory Bank 2 (FPGA) initialization */
|
|
#define CFG_EBC_PB2AP 0x9400C800
|
|
#define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000)
|
|
|
|
#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* GPIO Setup
|
|
*----------------------------------------------------------------------*/
|
|
#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
|
|
{ \
|
|
/* GPIO Core 0 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
|
|
{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
|
|
{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
|
|
{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
|
|
{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
|
|
{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
|
|
{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
|
|
{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
|
|
{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
|
|
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
|
|
} \
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Some Kilauea stuff..., mainly fpga registers
|
|
*/
|
|
#define CFG_FPGA_REG_BASE CFG_FPGA_BASE
|
|
#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 10))
|
|
|
|
/* interrupt */
|
|
#define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000
|
|
#define CFG_FPGA_SLIC0_W_DPRAM_INT 0x40000000
|
|
#define CFG_FPGA_SLIC1_R_DPRAM_INT 0x20000000
|
|
#define CFG_FPGA_SLIC1_W_DPRAM_INT 0x10000000
|
|
#define CFG_FPGA_PHY0_INT 0x08000000
|
|
#define CFG_FPGA_PHY1_INT 0x04000000
|
|
#define CFG_FPGA_SLIC0_INT 0x02000000
|
|
#define CFG_FPGA_SLIC1_INT 0x01000000
|
|
|
|
/* DPRAM setting */
|
|
/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */
|
|
#define CFG_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */
|
|
#define CFG_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */
|
|
#define CFG_FPGA_DPRAM_RW_TYPE 0x00080000
|
|
#define CFG_FPGA_DPRAM_RST 0x00040000
|
|
#define CFG_FPGA_UART0_FO 0x00020000
|
|
#define CFG_FPGA_UART1_FO 0x00010000
|
|
|
|
/* loopback */
|
|
#define CFG_FPGA_CHIPSIDE_LOOPBACK 0x00004000
|
|
#define CFG_FPGA_LINESIDE_LOOPBACK 0x00008000
|
|
#define CFG_FPGA_SLIC0_ENABLE 0x00002000
|
|
#define CFG_FPGA_SLIC1_ENABLE 0x00001000
|
|
#define CFG_FPGA_SLIC0_CS 0x00000800
|
|
#define CFG_FPGA_SLIC1_CS 0x00000400
|
|
#define CFG_FPGA_USER_LED0 0x00000200
|
|
#define CFG_FPGA_USER_LED1 0x00000100
|
|
|
|
#endif /* __CONFIG_H */
|