8a8d24bdf1
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
276 lines
6.9 KiB
C
276 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
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* One-Time-Programmable (OTP) memory used within the SiFive FU540.
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* It is documented in the FU540 manual here:
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* https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
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*
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* Copyright (C) 2018 Philipp Hug <philipp@hug.cx>
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* Copyright (C) 2018 Joey Hewitt <joey@joeyhewitt.com>
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*
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* Copyright (C) 2020 SiFive, Inc
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*/
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/*
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* The FU540 stores 4096x32 bit (16KiB) values.
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* Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
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* Right now first 1KiB is used to store only serial number.
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*/
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#include <common.h>
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#include <dm/device.h>
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#include <dm/read.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <misc.h>
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#define BYTES_PER_FUSE 4
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#define PA_RESET_VAL 0x00
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#define PAS_RESET_VAL 0x00
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#define PAIO_RESET_VAL 0x00
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#define PDIN_RESET_VAL 0x00
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#define PTM_RESET_VAL 0x00
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#define PCLK_ENABLE_VAL BIT(0)
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#define PCLK_DISABLE_VAL 0x00
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#define PWE_WRITE_ENABLE BIT(0)
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#define PWE_WRITE_DISABLE 0x00
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#define PTM_FUSE_PROGRAM_VAL BIT(1)
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#define PCE_ENABLE_INPUT BIT(0)
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#define PCE_DISABLE_INPUT 0x00
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#define PPROG_ENABLE_INPUT BIT(0)
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#define PPROG_DISABLE_INPUT 0x00
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#define PTRIM_ENABLE_INPUT BIT(0)
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#define PTRIM_DISABLE_INPUT 0x00
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#define PDSTB_DEEP_STANDBY_ENABLE BIT(0)
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#define PDSTB_DEEP_STANDBY_DISABLE 0x00
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/* Tpw - Program Pulse width delay */
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#define TPW_DELAY 20
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/* Tpwi - Program Pulse interval delay */
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#define TPWI_DELAY 5
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/* Tasp - Program address setup delay */
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#define TASP_DELAY 1
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/* Tcd - read data access delay */
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#define TCD_DELAY 40
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/* Tkl - clok pulse low delay */
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#define TKL_DELAY 10
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/* Tms - PTM mode setup delay */
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#define TMS_DELAY 1
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struct sifive_otp_regs {
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u32 pa; /* Address input */
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u32 paio; /* Program address input */
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u32 pas; /* Program redundancy cell selection input */
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u32 pce; /* OTP Macro enable input */
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u32 pclk; /* Clock input */
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u32 pdin; /* Write data input */
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u32 pdout; /* Read data output */
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u32 pdstb; /* Deep standby mode enable input (active low) */
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u32 pprog; /* Program mode enable input */
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u32 ptc; /* Test column enable input */
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u32 ptm; /* Test mode enable input */
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u32 ptm_rep;/* Repair function test mode enable input */
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u32 ptr; /* Test row enable input */
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u32 ptrim; /* Repair function enable input */
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u32 pwe; /* Write enable input (defines program cycle) */
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};
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struct sifive_otp_plat {
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struct sifive_otp_regs __iomem *regs;
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u32 total_fuses;
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};
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/*
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* offset and size are assumed aligned to the size of the fuses (32-bit).
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*/
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static int sifive_otp_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct sifive_otp_plat *plat = dev_get_plat(dev);
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struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
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/* Check if offset and size are multiple of BYTES_PER_FUSE */
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if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
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printf("%s: size and offset must be multiple of 4.\n",
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__func__);
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return -EINVAL;
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}
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int fuseidx = offset / BYTES_PER_FUSE;
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int fusecount = size / BYTES_PER_FUSE;
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/* check bounds */
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if (offset < 0 || size < 0)
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return -EINVAL;
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if (fuseidx >= plat->total_fuses)
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return -EINVAL;
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if ((fuseidx + fusecount) > plat->total_fuses)
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return -EINVAL;
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u32 fusebuf[fusecount];
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/* init OTP */
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writel(PDSTB_DEEP_STANDBY_ENABLE, ®s->pdstb);
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writel(PTRIM_ENABLE_INPUT, ®s->ptrim);
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writel(PCE_ENABLE_INPUT, ®s->pce);
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/* read all requested fuses */
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for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
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writel(fuseidx, ®s->pa);
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/* cycle clock to read */
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writel(PCLK_ENABLE_VAL, ®s->pclk);
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ndelay(TCD_DELAY * 1000);
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writel(PCLK_DISABLE_VAL, ®s->pclk);
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ndelay(TKL_DELAY * 1000);
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/* read the value */
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fusebuf[i] = readl(®s->pdout);
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}
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/* shut down */
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writel(PCE_DISABLE_INPUT, ®s->pce);
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writel(PTRIM_DISABLE_INPUT, ®s->ptrim);
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writel(PDSTB_DEEP_STANDBY_DISABLE, ®s->pdstb);
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/* copy out */
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memcpy(buf, fusebuf, size);
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return size;
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}
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/*
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* Caution:
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* OTP can be written only once, so use carefully.
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*
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* offset and size are assumed aligned to the size of the fuses (32-bit).
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*/
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static int sifive_otp_write(struct udevice *dev, int offset,
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const void *buf, int size)
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{
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struct sifive_otp_plat *plat = dev_get_plat(dev);
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struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
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/* Check if offset and size are multiple of BYTES_PER_FUSE */
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if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
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printf("%s: size and offset must be multiple of 4.\n",
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__func__);
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return -EINVAL;
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}
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int fuseidx = offset / BYTES_PER_FUSE;
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int fusecount = size / BYTES_PER_FUSE;
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u32 *write_buf = (u32 *)buf;
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u32 write_data;
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int i, pas, bit;
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/* check bounds */
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if (offset < 0 || size < 0)
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return -EINVAL;
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if (fuseidx >= plat->total_fuses)
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return -EINVAL;
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if ((fuseidx + fusecount) > plat->total_fuses)
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return -EINVAL;
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/* init OTP */
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writel(PDSTB_DEEP_STANDBY_ENABLE, ®s->pdstb);
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writel(PTRIM_ENABLE_INPUT, ®s->ptrim);
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/* reset registers */
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writel(PCLK_DISABLE_VAL, ®s->pclk);
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writel(PA_RESET_VAL, ®s->pa);
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writel(PAS_RESET_VAL, ®s->pas);
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writel(PAIO_RESET_VAL, ®s->paio);
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writel(PDIN_RESET_VAL, ®s->pdin);
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writel(PWE_WRITE_DISABLE, ®s->pwe);
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writel(PTM_FUSE_PROGRAM_VAL, ®s->ptm);
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ndelay(TMS_DELAY * 1000);
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writel(PCE_ENABLE_INPUT, ®s->pce);
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writel(PPROG_ENABLE_INPUT, ®s->pprog);
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/* write all requested fuses */
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for (i = 0; i < fusecount; i++, fuseidx++) {
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writel(fuseidx, ®s->pa);
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write_data = *(write_buf++);
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for (pas = 0; pas < 2; pas++) {
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writel(pas, ®s->pas);
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for (bit = 0; bit < 32; bit++) {
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writel(bit, ®s->paio);
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writel(((write_data >> bit) & 1),
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®s->pdin);
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ndelay(TASP_DELAY * 1000);
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writel(PWE_WRITE_ENABLE, ®s->pwe);
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udelay(TPW_DELAY);
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writel(PWE_WRITE_DISABLE, ®s->pwe);
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udelay(TPWI_DELAY);
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}
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}
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writel(PAS_RESET_VAL, ®s->pas);
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}
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/* shut down */
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writel(PWE_WRITE_DISABLE, ®s->pwe);
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writel(PPROG_DISABLE_INPUT, ®s->pprog);
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writel(PCE_DISABLE_INPUT, ®s->pce);
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writel(PTM_RESET_VAL, ®s->ptm);
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writel(PTRIM_DISABLE_INPUT, ®s->ptrim);
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writel(PDSTB_DEEP_STANDBY_DISABLE, ®s->pdstb);
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return size;
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}
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static int sifive_otp_of_to_plat(struct udevice *dev)
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{
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struct sifive_otp_plat *plat = dev_get_plat(dev);
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int ret;
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plat->regs = dev_read_addr_ptr(dev);
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ret = dev_read_u32(dev, "fuse-count", &plat->total_fuses);
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if (ret < 0) {
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pr_err("\"fuse-count\" not found\n");
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return ret;
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}
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return 0;
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}
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static const struct misc_ops sifive_otp_ops = {
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.read = sifive_otp_read,
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.write = sifive_otp_write,
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};
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static const struct udevice_id sifive_otp_ids[] = {
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{ .compatible = "sifive,fu540-c000-otp" },
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{}
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};
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U_BOOT_DRIVER(sifive_otp) = {
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.name = "sifive_otp",
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.id = UCLASS_MISC,
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.of_match = sifive_otp_ids,
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.of_to_plat = sifive_otp_of_to_plat,
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.plat_auto = sizeof(struct sifive_otp_plat),
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.ops = &sifive_otp_ops,
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};
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