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u-boot/drivers/fpga
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Tom Rini cbe607b920 Xilinx changes for v2021.04-rc3 
qspi:
 - Support for dual/quad mode
 - Fix speed handling
 
 clk:
 - Add clock enable function for zynq/zynqmp/versal
 
 gem:
 - Enable clock for Versal
 - Fix error path
 - Fix mdio deregistration path
 
 fpga:
 - Fix buffer alignment for ZynqMP
 
 xilinx:
 - Fix reset reason clearing in ZynqMP
 - Show silicon version in SPL for Zynq/ZynqMP
 - Fix DTB selection for ZynqMP
 - Rename zc1275 to zcu1275 to match DT name
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYDUezQAKCRDKSWXLKUoM
 IbtgAJ9jZ+BOtwFaHR19TENC2DsHTINnnwCfSDn3fU0OFJRI0HD7pRxXr4xrb3M=
 =Kr8x
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.04-rc3

qspi:
- Support for dual/quad mode
- Fix speed handling

clk:
- Add clock enable function for zynq/zynqmp/versal

gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path

fpga:
- Fix buffer alignment for ZynqMP

xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
2021-02-23 10:45:55 -05:00
..
ACEX1K.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
altera.c fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox 2020-10-09 17:53:12 +08:00
cyclon2.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
fpga.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
intel_sdm_mb.c arm: socfpga: soc64: Add ATF support for FPGA reconfig driver 2021-01-15 17:48:37 +08:00
ivm_core.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
Kconfig arm: socfpga: agilex: Enable FPGA Full Reconfiguration support 2020-10-09 17:53:12 +08:00
lattice.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
Makefile fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox 2020-10-09 17:53:12 +08:00
socfpga_arria10.c image: Adjust the workings of fit_check_format() 2021-02-15 22:31:52 -05:00
socfpga_gen5.c arm: socfpga: Convert system manager from struct to defines 2020-01-07 14:38:33 +01:00
socfpga.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
spartan2.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
spartan3.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
stratixII.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
stratixv.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
versalpl.c xilinx: zynqmp: synchronize firmware call return payload 2020-08-20 09:49:20 +02:00
virtex2.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
xilinx.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
zynqmppl.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
zynqpl.c fpga: zynqpl: fix buffer alignment 2021-02-23 14:56:55 +01:00