u-boot/board/micronas/vct/Kconfig
Paul Burton 372286217f MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:44:24 +02:00

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if TARGET_VCT
config SYS_BOARD
default "vct"
config SYS_VENDOR
default "micronas"
config SYS_CONFIG_NAME
default "vct"
config SYS_TEXT_BASE
default 0x87000000
config SYS_DCACHE_SIZE
default 16384
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 16384
config SYS_ICACHE_LINE_SIZE
default 32
menu "vct board options"
choice
prompt "Board variant"
optional
config VCT_PLATINUM
bool "Enable VCT_PLATINUM"
config VCT_PLATINUMAVC
bool "Enable VCT_PLATINUMAVC"
config VCT_PREMIUM
bool "Enable VCT_PLATINUMAVC"
endchoice
config VCT_ONENAND
bool "Enable VCT_ONENAND"
config VCT_SMALL_IMAGE
bool "Enable VCT_SMALL_IMAGE"
endmenu
endif