740820519c
There some vendor quirks for MTK xHCI 0.96 host controller: 1. It defines some extra SW scheduling parameters for HW to minimize the scheduling effort for synchronous and interrupt endpoints. The parameters are put into reserved DWs of slot context and endpoint context. 2. Its TDS in Normal TRB defines a number of packets that remains to be transferred for a TD after processing all Max packets in all previous TRBs. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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| .. | ||
| ci_udc.h | ||
| designware_udc.h | ||
| dwc2_udc.h | ||
| ehci-ci.h | ||
| fotg210.h | ||
| fusbh200.h | ||
| pxa27x_udc.h | ||
| udc.h | ||
| ulpi.h | ||
| xhci.h | ||