73ca0140e1
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Reference from below Linux commit,
commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
63 lines
1.5 KiB
C
63 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* include/dwc3-uboot.h
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*
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* Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
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*
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* Designware SuperSpeed USB uboot init
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*/
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#ifndef __DWC3_UBOOT_H_
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#define __DWC3_UBOOT_H_
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#include <generic-phy.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/phy.h>
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struct dwc3_device {
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unsigned long base;
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enum usb_dr_mode dr_mode;
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enum usb_phy_interface hsphy_mode;
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u32 maximum_speed;
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unsigned tx_fifo_resize:1;
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unsigned has_lpm_erratum;
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u8 lpm_nyet_threshold;
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unsigned is_utmi_l1_suspend;
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u8 hird_threshold;
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unsigned disable_scramble_quirk;
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unsigned u2exit_lfps_quirk;
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unsigned u2ss_inp3_quirk;
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unsigned req_p1p2p3_quirk;
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unsigned del_p1p2p3_quirk;
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unsigned del_phy_power_chg_quirk;
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unsigned lfps_filter_quirk;
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unsigned rx_detect_poll_quirk;
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unsigned dis_u3_susphy_quirk;
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unsigned dis_u2_susphy_quirk;
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unsigned dis_del_phy_power_chg_quirk;
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unsigned tx_de_emphasis_quirk;
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unsigned tx_de_emphasis;
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int index;
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};
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int dwc3_uboot_init(struct dwc3_device *dev);
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void dwc3_uboot_exit(int index);
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void dwc3_uboot_handle_interrupt(int index);
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struct phy;
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#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
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int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys);
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int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys);
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#else
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static inline int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
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{
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return -ENOTSUPP;
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}
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static inline int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
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{
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return -ENOTSUPP;
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}
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#endif
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#endif /* __DWC3_UBOOT_H_ */
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