7208396bbf
This reverts commit5d3a21df66, reversing changes made to56d37f1c56. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
257 lines
6.9 KiB
C
257 lines
6.9 KiB
C
/*
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* This code was extracted from:
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* git://github.com/gonzoua/u-boot-pi.git master
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* and hence presumably (C) 2012 Oleksandr Tymoshenko
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*
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* Tweaks for U-Boot upstreaming
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* (C) 2012 Stephen Warren
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*
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* Portions (e.g. read/write macros, concepts for back-to-back register write
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* timing workarounds) obviously extracted from the Linux kernel at:
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* https://github.com/raspberrypi/linux.git rpi-3.6.y
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*
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* The Linux kernel code has the following (c) and license, which is hence
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* propagated to Oleksandr's tree and here:
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*
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* Support for SDHCI device on 2835
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* Based on sdhci-bcm2708.c (c) 2010 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Supports:
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* SDHCI platform device - Arasan SD controller in BCM2708
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*
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* Inspired by sdhci-pci.c, by Pierre Ossman
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <sdhci.h>
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#include <time.h>
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#include <asm/arch/msg.h>
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#include <asm/arch/mbox.h>
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#include <mach/sdhci.h>
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#include <mach/timer.h>
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/* 400KHz is max freq for card ID etc. Use that as min */
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#define MIN_FREQ 400000
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#define SDHCI_BUFFER 0x20
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struct bcm2835_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct bcm2835_sdhci_host {
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struct sdhci_host host;
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uint twoticks_delay;
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ulong last_write;
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};
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static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host)
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{
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return (struct bcm2835_sdhci_host *)host;
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}
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static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val,
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int reg)
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{
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struct bcm2835_sdhci_host *bcm_host = to_bcm(host);
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/*
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* The Arasan has a bugette whereby it may lose the content of
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* successive writes to registers that are within two SD-card clock
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* cycles of each other (a clock domain crossing problem).
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* It seems, however, that the data register does not have this problem.
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* (Which is just as well - otherwise we'd have to nobble the DMA engine
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* too)
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*/
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if (reg != SDHCI_BUFFER) {
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while (timer_get_us() - bcm_host->last_write <
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bcm_host->twoticks_delay)
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;
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}
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writel(val, host->ioaddr + reg);
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bcm_host->last_write = timer_get_us();
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}
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static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
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{
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return readl(host->ioaddr + reg);
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}
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static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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bcm2835_sdhci_raw_writel(host, val, reg);
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}
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static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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static u32 shadow;
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u32 oldval = (reg == SDHCI_COMMAND) ? shadow :
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bcm2835_sdhci_raw_readl(host, reg & ~3);
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u32 word_num = (reg >> 1) & 1;
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u32 word_shift = word_num * 16;
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u32 mask = 0xffff << word_shift;
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u32 newval = (oldval & ~mask) | (val << word_shift);
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if (reg == SDHCI_TRANSFER_MODE)
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shadow = newval;
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else
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bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
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}
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static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3);
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u32 byte_num = reg & 3;
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u32 byte_shift = byte_num * 8;
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u32 mask = 0xff << byte_shift;
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u32 newval = (oldval & ~mask) | (val << byte_shift);
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bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
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}
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static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
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{
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u32 val = bcm2835_sdhci_raw_readl(host, reg);
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return val;
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}
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static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
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{
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u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
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u32 word_num = (reg >> 1) & 1;
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u32 word_shift = word_num * 16;
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u32 word = (val >> word_shift) & 0xffff;
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return word;
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}
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static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
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{
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u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
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u32 byte_num = reg & 3;
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u32 byte_shift = byte_num * 8;
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u32 byte = (val >> byte_shift) & 0xff;
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return byte;
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}
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static const struct sdhci_ops bcm2835_ops = {
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.write_l = bcm2835_sdhci_writel,
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.write_w = bcm2835_sdhci_writew,
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.write_b = bcm2835_sdhci_writeb,
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.read_l = bcm2835_sdhci_readl,
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.read_w = bcm2835_sdhci_readw,
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.read_b = bcm2835_sdhci_readb,
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};
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static int bcm2835_sdhci_bind(struct udevice *dev)
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{
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struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static int bcm2835_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
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struct bcm2835_sdhci_host *priv = dev_get_priv(dev);
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struct sdhci_host *host = &priv->host;
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fdt_addr_t base;
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int emmc_freq;
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int ret;
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int clock_id = (int)dev_get_driver_data(dev);
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base = devfdt_get_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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ret = bcm2835_get_mmc_clock(clock_id);
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if (ret < 0) {
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debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret);
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return ret;
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}
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emmc_freq = ret;
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/*
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* See the comments in bcm2835_sdhci_raw_writel().
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*
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* This should probably be dynamically calculated based on the actual
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* frequency. However, this is the longest we'll have to wait, and
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* doesn't seem to slow access down too much, so the added complexity
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* doesn't seem worth it for now.
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*
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* 1/MIN_FREQ is (max) time per tick of eMMC clock.
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* 2/MIN_FREQ is time for two ticks.
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* Multiply by 1000000 to get uS per two ticks.
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* +1 for hack rounding.
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*/
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priv->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1;
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priv->last_write = 0;
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host->name = dev->name;
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host->ioaddr = (void *)(uintptr_t)base;
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host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
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SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
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host->max_clk = emmc_freq;
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host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
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host->ops = &bcm2835_ops;
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ);
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if (ret) {
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debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret);
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return ret;
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}
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upriv->mmc = &plat->mmc;
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host->mmc->priv = host;
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return sdhci_probe(dev);
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}
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static const struct udevice_id bcm2835_sdhci_match[] = {
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{
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.compatible = "brcm,bcm2835-sdhci",
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.data = BCM2835_MBOX_CLOCK_ID_EMMC
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},
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{
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.compatible = "brcm,bcm2711-emmc2",
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.data = BCM2835_MBOX_CLOCK_ID_EMMC2
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(sdhci_cdns) = {
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.name = "sdhci-bcm2835",
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.id = UCLASS_MMC,
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.of_match = bcm2835_sdhci_match,
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.bind = bcm2835_sdhci_bind,
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.probe = bcm2835_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct bcm2835_sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct bcm2835_sdhci_plat),
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.ops = &sdhci_ops,
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};
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